JTAG download error to DDR

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JTAG download error to DDR

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terencenakada
Contributor II

I am creating tests for a customer's i.MX6Q board. We are having issues downloading data to DDR3 via JTAG. Our initialization script can properly initialize the DDR3 (RAM tests pass). We can download data to internal RAM. But, downloading via JTAG to DDR3 is unreliable. When it fails, it will fail at offsets of 0x4 and 0xc (only certain byte lanes will fail).

DATA 4 0x10000000 0x11223344 (read result = 0x11223344)

DATA 4 0x10000004 0x55667788 (read result = 0x55001688)

DATA 4 0x10000008 0x99AABBCC (read result = 0x99AABBCC)

DATA 4 0x1000000c 0xDDEEFF00 (read result = 0xDD001600)

CPU access to DDR is still okay and memory tests to DDR will pass. It is only JTAG access to DDR that seems to be affected.

Are there any i.MX6 configuration registers which would affect JTAG access to DDR?

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terencenakada
Contributor II

Hi Sinan,

I am using AHB memory access by default. I looked into options for switching to memory via core, but this also exhibited the same problem.

After more investigation, it appears that the customers board was in a secure state. I set ARM secure configuration register SCR.NS bit to put in non-secure mode and this seems to have resolved the issue.

Thank you,

Terence

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sinanakman
Senior Contributor III

Hi Terence

I wonder if you are accessing the memory via core or AHB access port.

I don't know what your probe is but I use a BDI3000 and I can define

the access type e.g. :

MEMACCES CORE 5 ; 40 TCK's access delay
MEMACCES AHB 4 ; access via AHB, 32 TCK delay

Perhaps making sure that your probe accesses memory via

core and adding access delays might make a difference.

Hope this helps.

Regards

Sinan Akman

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terencenakada
Contributor II

Hi Sinan,

I am using AHB memory access by default. I looked into options for switching to memory via core, but this also exhibited the same problem.

After more investigation, it appears that the customers board was in a secure state. I set ARM secure configuration register SCR.NS bit to put in non-secure mode and this seems to have resolved the issue.

Thank you,

Terence

View solution in original post

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wenmingfeng
Contributor III

Hi Terence,

I encounter the same issue, when I download a file into the ddr, I can only get the first word, others are all zeros.

Can you share the code to reset the SCR.NS bit?

thanks!

wenming

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Terence

one can try to decrease jtag frequency and check signals

with oscilloscope. Also please check Table 2-5. JTAG recommendations

i.MX6 System Development User’s Guide

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Best regards
igor
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terencenakada
Contributor II

Hi Igor,

I am able to download via JTAG to internal SRAM. So, it doesn't appear to be a signal or TCK issue. I can also read/write single words to DDR. It's only after a large download that the DDR access via JTAG has issues.

Thanks,

Terence

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Terence

it may be signal or TCK issue since DDR access
produces much more noise than internal iRAM.

Best regards
igor

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terencenakada
Contributor II

Hi Igor,

I tried at 500KHz and I still get the same results. I am able to download to internal SRAM at up to 15MHz.

Single reads/writes always seem to work before the download.  After the download, the failed byte lanes in addresses (at offsets 0x4 and 0xc) are stuck at their values. If I use some embedded code and have the CPU access those locations in DDR, it is successful. If I switch back to JTAG access to those locations, then the byte lanes are stuck in the last value. If I re-initialize the DDR, then single JTAG accesses work again.

So it seems to be a different issue than TCK or signal quality.

Any other ideas?

Thank you,

Terence

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