It can't use LAN function

[t2865k5]

Dear NXP,

We have a srg_imx8mplus platform (base imx8mplus). In this HW design, we have 2 LANs.
Now the functions of LAN1 and LAN2 are disabled. We check the hardware circuit is with
imx8mplus is the same. In Uboot mode, “Could not get PHY for FEC0:addr1” will appear.
I measure the MDC signal, MDC does not have a clock.

Can imx8mplus CPU provide clock to MDC?
How to modify the code?

[t2865k5]

Dear NXP,

(1) I check the u-boot_imx8mp-evk.dts (arch/arm/dts/imx8mp-evk.dts) and kernel-imx8mp-evk.dts (arch/arm64/boot/dts/freescale/imx8mp-evk.dts).

Their settings are the same as yours. Please help me to check them again if the settings of my two files are correct.

(2) 

MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3

MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91

Should these be LAN MDC clock settings?
Are there relevant documents that explain the meaning of these values?

[Zhiming_Liu]

Their are gpio setting value in i.MX8MP datasheet, i think you should check your hardware again because the evk can use two eth at the same time. It means the two rtl8211 chip is working at the same time.

[t2865k5]

Dear NXP,

The hardware engineer modified the hardware, LAN1 does not have a clock, and LAN2 has a clock. So LAN2 can work normally, but LAN1 can't work normally.

Does the default BSP code provide a setting of clocks to LAN1 and LAN2 MDC at the same time? Or provide two setting of clocks to MDC1/MDC2 separately?

Please tell me how to modify the code?

[Zhiming_Liu]

Does the default BSP code provide a setting of clocks to LAN1 and LAN2 MDC at the same time? Or provide two setting of clocks to MDC1/MDC2 separately?

--->yes,default BSP code provide two  MDC, they are two different pad.

pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC	0x3
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO	0x3
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x19
		>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
		>;
	};

[t2865k5]

Dear NXP,

Please call me how to set CPU clock to MDC.

[Zhiming_Liu]

Hi @t2865k5 

Default bsp can provide MDC clock.

[t2865k5]

Dear NXP ,

Code base:

repo init -u https://source.codeaurora.org/external/imx/imx-manifest -b imx-linux-gatesgarth -m imx-5.10.9-1.0.0.xml