Issue with DDR3 memory on custom i.MX6 board

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Issue with DDR3 memory on custom i.MX6 board

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alexandernovik2
Contributor II

I have some issues when I am trying to perform ddr stress test. How can I fix it? I have custom board with i.MX6q and 2 Gb RAM H5TQ4G63MFR-PBI (4 chips by 512 Mb). I found some useful information, but I don't know how to start.

i.MX6DQSDL DDR3 Script Aid 

https://community.nxp.com/docs/DOC-105652 

I found ddr-setup.cfg which almost all registers are set to 0x00000030

## Starting application at 0x00907000 ...

============================================
DDR Stress Test (2.6.0)
Build: Oct 24 2016, 15:21:46
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.5
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00002850
SRC_SBMR2(0x020d801c) = 0x2a000001
============================================

What ARM core speed would you like to run?
Type 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz
ARM Clock set to 800MHz

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
============================================

Current Temperature: 52
============================================

Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB
For maximum supported density (4GB), we can only access up to 3.75GB. Type 7 to select this
DDR density selected (MB): 512


Would do you want to change VDD_SOC_CAP/VDD_ARM_CAP voltage? Type 'y' to run and 'n' to skip


Would do you want run DDR Calibration? Type 'y' to run and 'n' to skip


The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same value
Would do you want run DDR Stress Test? Type 'y' to run and 'n' to skip

Enter desired START freq (135 to 672 MHz), then hit enter.
Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.
333
The freq you entered was: 333

Enter desired END freq (135 to 672 MHz), then hit enter.
Make sure this is equal to or greater than start freq
672
The freq you entered was: 672

Do you want to run DDR Stress Test for simple loop or Over Night Test?
Type '0' for simple loop. Type '1' for Over Night Test

DDR Stress Test Iteration 1
Current Temperature: 50
============================================

DDR Freq: 327 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Freq: 339 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Freq: 352 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Freq: 365 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Freq: 380 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Freq: 396 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Freq: 413 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Freq: 432 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Freq: 452 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Freq: 475 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
Address of bank1 failure: 0x16359940
Data initially read was: 0xFFFFFFDFFFFFFFFF
Data re-read is: 0xFFFFFFDFFFFFFFFF
But pattern was: 0xFFFFFFFFFFFFFFFF
Error: failed to run stress test!!!

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alexandernovik2
Contributor II

The problem was in the board layout. One of the lines on data bus was significantly longer than others. As it is a dummy board, I just cut the upper 1 GB DDR3 in the memory init script and the board becomes work.

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igorpadykov
NXP Employee
NXP Employee

Hi Alexander

please use script aid for custom board

i.MX6DQSDL DDR3 Script Aid 

https://community.nxp.com/docs/DOC-331528

error:

Data re-read is: 0xFFFFFFDFFFFFFFFF
But pattern was: 0xFFFFFFFFFFFFFFFF

means smth wrong with 37 bit, so one can attach jtag and

test signals on that line.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
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alexandernovik2
Contributor II

Thank you, Igor. I tried to use DD3 Script Aid, but I can't perform DDR calibration. I found MR1 in initialize script

MX6_IOM_DDRMODE_CTL 0x00020000

When I tried to calibrate DDR, the stress test program asked me to enter MR1 value. Which value I need to enter?


============================================
DDR Stress Test (2.6.0)
Build: Oct 24 2016, 15:21:46
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.5
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00002850
SRC_SBMR2(0x020d801c) = 0x2a000001
============================================

What ARM core speed would you like to run?
Type 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz
ARM Clock set to 800MHz

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
============================================

Current Temperature: 52
============================================

Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB
For maximum supported density (4GB), we can only access up to 3.75GB. Type 7 to select this
DDR density selected (MB): 512


Would do you want to change VDD_SOC_CAP/VDD_ARM_CAP voltage? Type 'y' to run and 'n' to skip

Please select VDD_SOC_CAP volatage on the board
Type 0 for 1.15V; 1 for 1.175V; 2 for 1.2V; 3 for 1.225V; 4 for 1.25V; 5 for 1.275V; 6 for 1.3V
VDD_SOC_CAP option: 2

Please select VDD_ARM_CAP volatage on the board
Type 0 for 1.15V; 1 for 1.175V; 2 for 1.2V; 3 for 1.225V; 4 for 1.25V; 5 for 1.275V; 6 for 1.3V
VDD_ARM_CAP option: 2


Would do you want run DDR Calibration? Type 'y' to run and 'n' to skip

Calibration will run at DDR frequency 528MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
Please enter the MR1 value on the initilization script
This will be re-programmed into MR1 after write leveling calibration
Enter as a 4-digit HEX value, example 0004, then hit enter
0000DDR Freq: 528 MHz

ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00010001
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00010001
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x00010001
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x001F001F
Write DQS delay result:
Write DQS0 delay: 1/256 CK
Write DQS1 delay: 1/256 CK
Write DQS2 delay: 1/256 CK
Write DQS3 delay: 1/256 CK
Write DQS4 delay: 1/256 CK
Write DQS5 delay: 1/256 CK
Write DQS6 delay: 31/256 CK
Write DQS7 delay: 31/256 CK

Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x11111111
. HC_DEL=0x00000001 result[01]=0x11111111
. HC_DEL=0x00000002 result[02]=0x11111111
. HC_DEL=0x00000003 result[03]=0x00010000
. HC_DEL=0x00000004 result[04]=0x00010000
. HC_DEL=0x00000005 result[05]=0x11111111
. HC_DEL=0x00000006 result[06]=0x11111111
. HC_DEL=0x00000007 result[07]=0x11111111
. HC_DEL=0x00000008 result[08]=0x11111111
. HC_DEL=0x00000009 result[09]=0x11111111
. HC_DEL=0x0000000A result[0A]=0x11111111
. HC_DEL=0x0000000B result[0B]=0x11111111
. HC_DEL=0x0000000C result[0C]=0x11111111
. HC_DEL=0x0000000D result[0D]=0x11111111
ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration

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igorpadykov
NXP Employee
NXP Employee

suggested for reading above presentation on p.19

recommends MR1=4

Best regards
igor

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alexandernovik2
Contributor II

I configured ddr-setup.cfg with values from aid for custom board. But I can't start calibration on 528 MHz, despite I can do it on ~333 MHz. MR1 = 4

ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00010001
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00010001
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x00010001
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x001F001F
Write DQS delay result:
Write DQS0 delay: 1/256 CK
Write DQS1 delay: 1/256 CK
Write DQS2 delay: 1/256 CK
Write DQS3 delay: 1/256 CK
Write DQS4 delay: 1/256 CK
Write DQS5 delay: 1/256 CK
Write DQS6 delay: 31/256 CK
Write DQS7 delay: 31/256 CK

Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x11111111
. HC_DEL=0x00000001 result[01]=0x11111111
. HC_DEL=0x00000002 result[02]=0x00111111
. HC_DEL=0x00000003 result[03]=0x00010000
. HC_DEL=0x00000004 result[04]=0x00010000
. HC_DEL=0x00000005 result[05]=0x11111111
. HC_DEL=0x00000006 result[06]=0x11111111
. HC_DEL=0x00000007 result[07]=0x11111111
. HC_DEL=0x00000008 result[08]=0x11111111
. HC_DEL=0x00000009 result[09]=0x11111111
. HC_DEL=0x0000000A result[0A]=0x11111111
. HC_DEL=0x0000000B result[0B]=0x11111111
. HC_DEL=0x0000000C result[0C]=0x11111111
. HC_DEL=0x0000000D result[0D]=0x11111111
ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration

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