Hello,
I am currently working on enabling multiple cores on my NXP platform and have encountered an issue when trying to set the entry point for the secondary cores to an address in DDR memory.
Context:
Primary Binary:
The primary binary is located in TCM memory at address 0x7e1000.
With the primary binary, the cores are enabled correctly, and even resets are handled properly.
Secondary Binary:
The secondary binary is located in DDR memory at address 0x40200000.
When I set the entry point for the secondary cores to the DDR address (0x40200000), the cores do not enable as expected.
Observations:
The primary binary works flawlessly when using the TCM memory address as the entry point.
When attempting to switch the entry point to the DDR address in the secondary binary, the cores do not initialize as expected.
I have ensured that the memory in DDR is correctly set up and that the code is properly located at the given address.
Questions:
Is there any known limitation or requirement that restricts the secondary cores from using an entry point in DDR memory instead of TCM?
Are there specific configurations or permissions (e.g., MPU/MMU settings, cache handling) that I need to adjust to allow the cores to start from a DDR address?
Could there be any differences in how the boot process handles entry points in DDR versus TCM, such as cache coherency or alignment requirements?
Any guidance or insights on how to configure the system to use a DDR address as the entry point for enabling multiple cores would be greatly appreciated.
Technical Details:
Primary binary address: 0x7e1000 (TCM) – Works fine for enabling cores.
Secondary binary address: 0x40200000 (DDR) – Cores do not enable.
Platform: NXP (IMX8MMINI.)
