Is there some restriction to input clock to i.MX6DQ CLKx_P/CLKx_N?

[satoshishimoda]

Hi community,

I havea a question about i.MX6DQ clock input.

I want to confirm whether there is some restrict to input clock to CLKx_P/CLKx_N.

(e.g. min xxx MHz, max yyy MHz, tolerance: zzz ppm or better)

Would you let me know it?

Best Regards,

Satoshi Shimoda

[Yuri · Accepted solution]

Hello,

  From the Hardware Development Guide :

"CLK1_P/CLK1_N and CLK2_P/CLK2_N are LVDS

input/output differential pairs compatible with

TIA/EIA-644 standard. The frequency range is 0 to

600 MHz.

Alternatively, a single-ended signal can be used to

drive a CLKx_P input. In this case, the corresponding

CLKx_N input should be tied to a constant voltage

level equal to 50% of VDD_HIGH_CAP. Termination

should be provided with high-frequency signals.

See the LVDS pad electrical specification in the data

sheet for further details."

Have a great day,
Yuri

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