Is there any official documents that JTAG debugger can not use at the time LMEM cache is enabled.

[hideo_yamashiro]

Hello,

I am searching any official documents that JTAG debugger can not use at the time LMEM cache is enabled on M4 core in i.mx7d.

I would like to get any official documents related the issue as a evidence.

On my result, I can not use JTAG debugger (uVision5 + ULINK pro) only at the time LMEM cache is enabled.

When LMEM cache is disabled, the debugger is working without any problems although the program is put on DDR-RAM(0x80000000-0x801FFFFF) or OCRAM(0x20220000-0x2023FFFF).

Best regards,

Hideo Yamashiro.

[Yuri]

@hideo_yamashiro 
Hello,

   We do not have special official documents regarding the JTAG debugger problem with M4
cache of i.MX7D enabled. There is the following explanation of such behavior:

"The J-Link sets breakpoints [BPs] in RAM via the Cortex-M specific AHB (background memory
access). This enables the J-Link to set soft BPs  w/o halting the core.
But this bypasses the cache. Consequently, this leads to erroneous behavior." 

  Note, it can be just implementation specific feature.

Regards,
Yuri.

[hideo_yamashiro]

Dear Yuri.

Thank you for your reply.

You mean the implementation of LMEM cahce is a specification of M4 core in i.mx7d.

The following behavior happens?
(1).A debugger puts a BKPT instraction at a point that the debugger's user sets.
(2).The user runs the program and the program stops at the point that a BKPT instruction is put.
(3).The user re-runs the program but the program execution stops at same point.
Because the CPU(M4 core) fetchs the BKPT instruction from cache buffer, not from memory.
The reason is that the BKPT instruction exists on LMEM cache
although the debugger modifies the BKPT instruction to the original instruction via AHB(background memory access).

Is my understanding is correct?

Best regards,
Hideo Yamashiro.

[Yuri · Accepted solution]

@hideo_yamashiro 
Hello,

   Yes, Your understanding is correct.

Regards,
Yuri.