I'll building a custom board with i.MX7ULP.
I understand that the wiring of each DDR signal line (the wiring from the CPU BGA pad to the DDR BGA pad) must be of equal length.
Is there any information about the wiring length inside the CPU (the wiring length from the DDR controller inside the CPU to the BGA PAD) ?
Or is there any calculation tool of DRAM bus length for i.MX7ULP ?
I found following check sheet but it's for i.MX6.
It is recommended to use section 3.4.1 (DDR routing rules) of the
Hardware Development Guide for the i.MX 7ULP.
It is quite enough for practical purposes.