Is there a reason SDCKE 0 is paired with CLK1 rather than CLK0?

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Is there a reason SDCKE 0 is paired with CLK1 rather than CLK0?

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katrinagundal-z
Contributor I

Looking at the multiple reference designs including the sabre board (dual-lite), the DRAM appears to be using the CLK1 clock pair with SDCKE0. Is there a reason SDCKE 0 is paired with CLK1 rather than CLK0?

We were unable to find an explanation in the chip documentation so if you could provide further info it would be greatly appreciated. We are trying to close out a design review...

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Yuri
NXP TechSupport
NXP TechSupport

The SDRAM clock signals are the same, assuming that the clock delays are the same.

Please look at section 44.12.53 [MMDC PHY CK Control Register (MMDCx_MPSDCTRL)]

of the Reference Manual [IMX6DQRM(Rev.2)] and section 17 (Clock Delay Calibration) of the

app note AN4467 about registers MMDC1_MPSDCTRL and MMDC2_MPSDCTRL, which are named

as SDCTRL[SDCLK0_DEL] and SDCTRL[SDCLK1_DEL] in the app note.

Regards,

Yuri.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Katrina

CLK1 and CLK0 clock are the same signals, so

no difference which to use.

Best regards

igor

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