Hello,
I use the RGMII interface of my i.MX6Q to connect a 100Mbps PHY. Currently I generate a 125MHz clock by the ANATOP (Analog Ethernet PLL) put it out on GPIO16 (GPIO7_IO11 -> Ball R2) do a wire connection between GPIO16 and ENET_REF_CLK (GPIO1_IO23 -> Ball V22) and feed the MAC.
Is it possible to route the 125MHz interally to the ENET_REF_CLK?
In RMII mode this is possible. Hardware Development Guide 12.4.1:

I my opinion the block labeled "ENET" is different from the ENET_REF_CLK which is used in RGMII mode. I don't need the 125MHz outside the i.MX6.