Hi, @haryanl
on i.MX8MP, we enable the WDQSEXTENSION feature of the DDR PHY whose description is as follows:
When set, DQS_T and DQS_C will be driven differentially to 0 and 1, respectively,
before and after a write burst, except during a memory read transaction.
From that I understand that DQS should be driven low at all times except a memory read transaction.
Here is measured the behavior of the system on 8MP EVK when WDQSEXTENSION is enabled and disabled:
