Is DDR2 Input AC Timing of IMX28CEC correct?

[hikaruuruno]

Dear Community,

We just noticed that the Table 36. DDR2 Input AC Timing is quite narrow.
For example, when the EMI clock is 200MHz, the range of input skew is 0.4 - 0.75ns and the range of input hold time is 2.0 - 2.25ns. (IMX28CEC Rev.3, 07/2012)

In contrast, the same parameters of i.MX50 are not so strict. (e.g. IMX50CEC does not define minimum input skew and maximum input hold time.)

In our board, tDQSQ of all DQ signals were ca. 0ns, definitely out of the range.

But the board is working well and memory test program (mtest) shows no error.
So we are suspecting that the data shown in IMX28CEC is wrong.
Does anyone know anything about it?

Thank you,
Hikaru Uruno

[Yuri]

Hello,

   As for the DDR2 timings of the i.MX28 : right now we do not have more

data, than provided in the Datasheet. In the future the timings may be

corrected, but I am afraid it will take some time.

   The actual timing may vary depending on software settings. What is actually
important for the controller is DDR22-DDR2, which results in the minimum required
DQ valid window width: 0.75ns + 0.5ns = 1.25ns of minimum width.

Have a great day,
Yuri

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[hikaruuruno]

Hi Yuri,

Thank you for your reply.

I see that there is no information whether the data is wrong or not.

I'm not sure I can convince the design reviewers in our company with your comment about the minimum required DQ valid window. But at least I have something to say now.

Best regards,

Hikaru