Inverting polarity for data i clock lines for PCIe for IMX6

[semirfazlagic]

We are building one PCIe interface with Gigabit PCIe RGMII chip I210 where IMX6 is master.

I got that our data (Rx, TX) and also CLK comming from IMX6 are with inverted polarity in our PCB.

I know that generally PCIe standard should  allow inverting polarity for data but i am not sure for CLK.

Also I am not sure if it is valid for IMX6.

My question is:

Can I neglect data and clock polarity for both Data lines and CLK for IMX6 based PCIe system.

Thank in advance

[Yuri]

Hello,

    IMX6 PCIe has no ability to configure signals polarity in software.

Nevertheless, HW Design Checking List for i.Mx6DQSDL contains useful recommendations

about using (external) PCIe clock :

"Due to CLKx_P/N is LVDS port and don't match with PCIe reference clock specification.

For PCIe Gen1 application, following low cost solution can be used(DC bias and AC

impedance should be considered).  Please refer to "HW Design Checking List for i.Mx6DQSDL
Rev2.9.xlsx", sheet "Schematic", Ref12 for more info."

  "PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip can't pass PCIe

Gen2 compliance test.  Recommend using external PCIe 2.0/3.0 clock generator with 2 HCSL
outputs solution. One clock channel connect to i.MX6 as a reference input, please click Ref14
("HW Design Checking List for i.Mx6DQSDL Rev2.9.xlsx") for reference circuit.

Another clock channel should connect to PCIe connector, please contact generator vendor

for detailed design guide."

< https://community.freescale.com/docs/DOC-93819 >

Have a great day,
Yuri

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[semirfazlagic]

Hi Yuri

Thank for answer.

Ok concerning CLK, but what about data ?

For example, I suppose that my Tx line (out from IMX6) can be swapped (polarity) because this pair goes

to I210 (PCI ethernet chip)  which supports polarity swapping and it is his responsability..

But, what about RX ( input from I210 to IMX6). I am not sure if also IMX6 supports it.

Officially should support, but I am afraid to make "stuppid" error.

Now, really my, data pairs (both Rx and TX) make  "nasty path" (minus and plus signals overlapping)

and I want to avoid if if possible. I know that signal integrity here is important.

Regards

[Yuri]

Hello,

According to PCIe specs regarding Link Initialization and Training

PCIe receiver can define Lane polarity inversion automatically.
I.MX6 PCIe_PHY supports PCIe specs (gen 2 and gen 1)

Regards,

Yuri.

[semirfazlagic]

Ok Yuri

Thank you very much. I expected this but want to be sure

Thank one more

Regards

From:

Yuri <admin@community.freescale.com>

To:

Semir Fazlagic <semir.fazlagic@exorint.it>

Date:

02/12/2016 04:40 AM

Subject:

Re: - Inverting polarity for data i clock lines for PCIe

for IMX6

NXP Community

Inverting polarity for data i clock lines for PCIe for IMX6

reply from Yuri Muhin in i.MX Community - View the full discussion

Hello,

According to PCIe specs regarding Link Initialization and Training

PCIe receiver can define Lane polarity inversion automatically.

I.MX6 PCIe_PHY supports PCIe specs (gen 2 and gen 1)

Regards,

Yuri.

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Semir Fazlagic

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