Interrupt counter of mxs-auart via ioctl() always zero

[lategoodbye]

Hello, i'm using 1 UART of the MX28 (mxs-auart) for serial protocols like M-Bus and it works fine.

In some situations it's important to know how many parity errors or something appeared one a interface. But i'm unable to get this information.

I tried the following to simulate a transmit:

# echo "1" > /dev/ttySP3

After that i expect that the transmit interrupt counter increase, but it doesn't happen:

# cat /proc/tty/driver/auart
serinfo:1.0 driver revision:
0: uart:mxs-auart.0 mmio:0x8006A000 irq:112 tx:0 rx:0 CTS
1: uart:mxs-auart.1 mmio:0x8006C000 irq:113 tx:0 rx:0 CTS
2: uart:mxs-auart.2 mmio:0x8006E000 irq:114 tx:0 rx:0 CTS
3: uart:mxs-auart.3 mmio:0x80070000 irq:115 tx:0 rx:0 RTS|CTS|DTR
4: uart:mxs-auart.4 mmio:0x80072000 irq:116 tx:0 rx:0 RTS|CTS|DTR

I've also written a small C program to read the interrupt counter TIOCGICOUNT via ioctl, but the important values are always zero:

Flags:
CTS: 0
DSR: 0
RING: 0
DCD: 0
Rx: 0
Tx: 0
Frame: 0
Overrun: 0
Parity: 0
Break: 0
Overflow: 0

At my point of view this is a bug in mxs-auart.

Does anybody knows a workaround or a trick to get this information?

[lategoodbye]

Implementing a M-Bus slave under Linux without real time would be hard, because of the timings. I heard IRQ has better latency than DMA, so it won't get better by changing it to DMA.

Maybe you can experiment a little with the low_latency flag of setserial.

Or you can try to reduce FIFO size.

[Royaz]

sorry for the late response.

Which M-Bus role should the imx take place (Master, Slave, Both)?

The Imx is the slave.

Which kernel version do you use (Freescale, Mainline)?

freescale.

How is your auart configured (DMA/IRQ mode)?

currently not DMA - i think I need to change it to DMA. but then I do not receive the interrupts like in IRQ. 

In which scenario do you need the break handling?

Our mbus is probably some kind of a private case. in few words it has an arbiter which divide the time between all participants. in order to do so it uses the break mechanism to to sync everyone. the next byte after the break indicates the address of the next node to transmit.  

How much too late does the break signal arrives?

when I have 250us between the breaks I loose the next character.

Do you use POSIX C with termios?

I am using a linux driver for mbus someone else wrote base on serio framework.

Can you post the patch for break interrupt support?

I am attaching the patch see SERIO_FRAME which is the interface to the linux drivers which handles the mbus protocol.

Thanks.

Roy

[lategoodbye]

Hello Roy,

let me ask some questions for better understanding.

Which M-Bus role should the imx take place (Master, Slave, Both)?

Which kernel version do you use (Freescale, Mainline)?

How is your auart configured (DMA/IRQ mode)?

In which scenario do you need the break handling?

How much too late does the break signal arrives?

Do you use POSIX C with termios?

Can you post the patch for break interrupt support?

[Royaz]

Hello Stefan,

I am trying to implement m-bus protocol on  the IMX.  I added to the mxs_auart.c support for the break interrupt needed for the syncing of the mbus protocol. I am able to receive the characters from the serial line. my problem is the sometime the break signal arrives too late and I am late reading the following character. I understand I need somehow to make the break interrupt more efficient. have you done something similar on the IMX ?  can you give some directions ?

thanks,

Roy Azriel 

[lategoodbye]

Here is the patch against Linux 2.6.35 from Freescale BSP.

[lategoodbye]

Okay, the problem is that the interrupt counter for Tx and Rx in mxs-auart from the Freescale BSP aren't incremented.

In the mainline kernel this problem doesn't exists. So i ported the counter handling back and create a patch.

Poorly the counter for parity errors and so on are still always zero.