Hi Igor,
Thanks for your kind support.
Using git cherry pick I have applied usb patches from u-boot 2020.04 and tested using few of the USBs(like Sandisk, Kingston). To test this recursively I made changes in
u-boot in such way it reboots after copy file from USB. Kept over night testing. Likewise tested many times. The USB intermittent issue seen still.
From debugs it was observed that, every time when issue was seen it was failed during first blocks transfer.
The error pattern is :
EHCI timed out on TD - token=0x1f8c80
EHCI timed out on TD - token=0x2008d80
EHCI timed out on TD - token=0xd8d80
EHCI timed out on TD - token=0x80008d80
EHCI timed out on TD - token=0x80008d80
EHCI timed out on TD - token=0x80008d80
EHCI timed out on TD - token=0x1f8c80
EHCI timed out on TD - token=0x128d80
EHCI timed out on TD - token=0xd8d80
EHCI timed out on TD - token=0x80008d80
EHCI timed out on TD - token=0x80008d80
EHCI timed out on TD - token=0x80008d80
My analysis for above pattern :
31 | 30:16 | 15 | 14:12 | 11:10 | 9:8 | 7:0 |
0 | 000000000011111 | 1 | 000 | 11 | 00 | 10000000 |
7th bit is set : qTD has been initialized and is ready to use. Enables the execution of transactions by the host controller.
9:8 are 00 : OUT token (generates token 0xE1)
11:10 are 11 : The host controller decrements the count for each consecutive error and writes it back to the qTD if the transaction fails. Write this field as 0x3, to allow up to three retries for the transfer.
14–10 bits are set to 000
15 bit is 1 : bit is set, when this qTD is completed, the host controller should issue an interrupt at the next interrupt threshold. Actually here qTD is not completed, not sure why this bit is set
30:16 bits are 000000000011111 : the 31 bytes to be moved with this transfer descriptor transfer.
31 bit is 0 : It is cleared for SETUP packets.
31 | 30:16 | 15 | 14:12 | 11:10 | 9:8 | 7:0 |
0 | 000001000000000 | 1 | 000 | 11 | 01 | 10000000 |
7th bit is set : qTD has been initialized and is ready to use. Enables the execution of transactions by the host controller
9:8 are 01 : IN token (generates token 0x69)
11:10 are 11 : The host controller decrements the count for each consecutive error and writes it back to the qTD if the transaction fails. Write this field as 0x3, to allow up to three retries for the transfer.
14–10 bits are set to 000
15 bit is 1 : bit is set, when this qTD is completed, the host controller should issue an interrupt at the next interrupt threshold. Actually here qTD is not completed, not sure why this bit is set
30:16 bits are 000001000000000: the 512 bytes to be moved with this transfer descriptor transfer.
31 bit is 0 : It is cleared for SETUP packets.
31 | 30:16 | 15 | 14:12 | 11:10 | 9:8 | 7:0 |
0 | 000000000001101 | 1 | 000 | 11 | 01 | 10000000 |
7th bit is set : qTD has been initialized and is ready to use. Enables the execution of transactions by the host controller
9:8 are 01 : IN token (generates token 0x69)
11:10 are 11 : The host controller decrements the count for each consecutive error and writes it back to the qTD if the transaction fails. Write this field as 0x3, to allow up to three retries for the transfer.
14–10 bits are set to 000
15 bit is 1 : bit is set, when this qTD is completed, the host controller should issue an interrupt at the next interrupt threshold. Actually here qTD is not completed, not sure why this bit is set
30:16 bits are 000000000001101: the 13 bytes to be moved with this transfer descriptor transfer.
31 bit is 0 : It is cleared for SETUP packets.
- token=0x80008d80 : this repeats 3times
31 | 30:16 | 15 | 14:12 | 11:10 | 9:8 | 7:0 |
1 | 000000000000000 | 1 | 000 | 11 | 01 | 10000000 |
7th bit is set : qTD has been initialized and is ready to use. Enables the execution of transactions by the host controller
9:8 are 01 : IN token (generates token 0x69)
11:10 are 11 : The host controller decrements the count for each consecutive error and writes it back to the qTD if the transaction fails. Write this field as 0x3, to allow up to three retries for the transfer.
14–10 bits are set to 000
15 bit is 1 : bit is set, when this qTD is completed, the host controller should issue an interrupt at the next interrupt threshold. Actually here qTD is not completed, not sure why this bit is set
30:16 bits are 000000000000000: If the value of this field is zero when the host controller fetches this transfer descriptor (and the active bit is set), the host controller executes a zero-length transaction and retires the transfer descriptor.
31 bit is 1: . This bit is set for IN and OUT transactions.
- token=0x1f8c80 : same as above
31 | 30:16 | 15 | 14:12 | 11:10 | 9:8 | 7:0 |
0 | 000000000010010 | 1 | 000 | 11 | 01 | 10000000 |
7th bit is set : qTD has been initialized and is ready to use. Enables the execution of transactions by the host controller
9:8 are 01 : IN token (generates token 0x69)
11:10 are 11 : The host controller decrements the count for each consecutive error and writes it back to the qTD if the transaction fails. Write this field as 0x3, to allow up to three retries for the transfer.
14–10 bits are set to 000
15 bit is 1 : bit is set, when this qTD is completed, the host controller should issue an interrupt at the next interrupt threshold. Actually here qTD is not completed, not sure why this bit is set
30:16 bits are 000000000010010 : the 18 bytes to be moved with this transfer descriptor transfer
31 bit is 0 : It is cleared for SETUP packets.
- token=0xd8d80 : same as above
- token=0x80008d80 : same as above. This repeats 3 time
The above shown pattern all token ID's Active bit(7th bit) is set, means qTD had been initialized and was ready to use but transaction was failed. So it went for retries, it repeated 3 times(see 11:10 bits are 11). Not clear about root cause of the issue to fix.
Thank you,
Jaya