Interfacing KSZ9131Rnxi to iMX 8M Nano

[Elias_M]

Hi, 

I want to operate the KSZ9131RNxi with the iMx8M Nano SOM in our carrier Board. the driver of the phy and the fec mac are loading proprely but I do get the communication just at 10Mbits and only when I type the following after OS Boot up :

$ ethtool -s eth0 speed 10 duplex full

The PHY is wired to operate in RGMII mode and with a speed of 1000Mbit/S.

How to solve this issue to operate the phy without using to type this command after boot up  ? and why 100Mbits and 1000Mbits is not working?

I would be very thankful for your contributions.

[Chavira]

Hi @Elias_M,
Thank you for contacting NXP Support!

How are you setting this up in the device tree?

I believe this issue can be resolved with a correct device tree configuration.
Could you please share your device tree file so I can review it?

If sharing it is not possible, you can refer to the examples provided in the following link

Best regards,
Chavira

[Elias_M]

Hi @Chavira ,

Thank you for your support.

Hier is how the fec device tree in Linux described: 

&fec1 {

fsl,magic-packet;

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_fec1_gpio>,

                   <&pinctrl_fec1>;

phy-mode = "rgmii-id";

phy-handle = <&ethphy0>;

phy-supply = <&reg_3v3_eth0>;

status = "okay";

mdio {

#address-cells = <1>;

#size-cells = <0>;

ethphy0: ethernet-phy@0 {

compatible = "ethernet-phy-ieee802.3-c22";

reg = <0>;

interrupt-parent = <&gpio5>;         

interrupts = <2 IRQ_TYPE_LEVEL_LOW>;  

micrel,led-mode=<1>;

};

};

};

reg_3v3_eth0: regulator-ethphy {

compatible = "regulator-fixed";

off-on-delay=<500000>;

regulator-always-on;

regulator-boot-on;

regulator-min-microvolt = <3300000>;

regulator-max-microvolt = <3300000>;

regulator-name = "3v3_eth0";

startup-delay-us = <200000>;

};

pinctrl_fec1_gpio: fec1gpiogrp {

fsl,pins = <

/* PHY interrupt */

MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2           0x19

>;

};

pinctrl_fec1: fec1grp {

fsl,pins = <

MX8MN_IOMUXC_ENET_MDC_ENET1_MDC                              0x3

MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO                            0x3

MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3                     0x1f

MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2                     0x1f

MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1                       0x1f

MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0                    0x1f

MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3                   0x91

MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2                   0x91

MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1                     0x91

MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0                  0x91

MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC                  0x1f

MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC                 0x91

MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91

MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f

>;

};

[Chavira]

Hi @Elias_M, 

For a better understanding I need to check the entire device tree file.

Best regards,
Chavira