Hi,
I'm doing bare metal coding on an SOC containing an I.MX6 ULL. I've going through the NXP Applications Processor Reference Manual for this processor and can find no details on the L2 cache controller, like its mmio address or the controller name. Is it a PL310 controller similar to an A9 processor?
Thanks for any insight you can give me.
Bob
Hello,
I.MX 6ULL does not have separate L2 cache controller / module.
L2 is just part of core.
Have a great day,
Yuri
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