Info on the i.MX53 pop memory devices

[marshachang]

Thought I would share this information:

Micron LPDDR2 168b 12x12 PoP (all x32 data width)

Qualified for Production at Micron

2Gbit –                 MT42L64M32D1KL-3 IT :A (667 MT/s)

                                MT42L64M32D1KL-2.5 IT :A (800 MT/s)

4Gbit –                 MT42L128M32D2KL-3 IT :A

                                MT42L128M32D2KL-2.5 IT :A

8Gbit –                 MT42L256M32D4KP-3 IT :A

                                MT42L256M32D4KP-2.5 IT :A

Please see the following link for a datasheet for the parts listed above.  Since they are all based on the same monolithic DRAM device, one datasheet covers all.

http://www.micron.com/parts/dram/mobile-ddr2-sdram/~/media/Documents/Products/Data%20Sheet/DRAM/5167...

[Chris1z]

Hi Marsha,

The MT42L128M32D2 part is going EOL and we need to replace it in our design.  Have you qualified a replacement? MT42L128M32D1 for example?

Thanks,

Chris

[GatorBoz]

Marsha,

On the  SCIMX538DZK1C (iMX538, PoP Package), there is only 1 POP_ZQ pin (pin P1), but the MT42L256M32D4KP-2.5IT:A (256M32, 168 ball PoP memory) has 2 POP_ZQ pins  (pin P1 and AC11). On the SCIMX538DZK1C pin AC11 (top) is to POP_VACC.

I need to know if the MT42L256M32D4KP-2.5IT:A will truly work with the SCIMX538DZK1C, or if we are limited to PoP parts that only have 1 ZQ pin.

Thanks.

[NitinSonar]

Hi Marsha,

This sounds intresting.

Is there any design guidelines you have for interfacing PoP memory with i.MX53?

Please reply.

Best Regards

Nitin Sonar