Inconsistent results on DDR calibration for custom i.MX6ULL board using DDR stress tester v2.70

[chadwolter]

Hi,

We are currently doing evaluation testing on a custom board utilizing an i.MX6ULL with 512MB of DDR3.  Using the "ddr_stress_tester_v2.70" tool from NXP and putting the board in Serial Downloader mode, and with the attached custom script, the Calibration test is run with the settings indicated by the attached screenshot.  The issue I am having is that when I run the calibration, and make the recommended settings to the *.inc file, and run the calibration again, it suggests different settings than it did during the previous run, which causes me to not trust what the tool is telling me.  Steps used are:

1.  Run the tester with the default *.inc file included with the tool (EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2.inc)

2.  Using the settings from the attached screenshot, run the calibration test

3.  Put the calibrations into the custom *.inc file (attached)

4.  Run the calibration again, using settings from the attached screenshot

5.  Suggested calibrations are different than those recommended in step 2

As an illustration, I ran several iterations and recorded one particular register:  MPWLDECTRL1.  Initially, the tool suggested a value of 0x001F001F for this register.  I then modified the setmem /32 0x021B0810 line in the *.inc file to reflect this.  I ran the calibration again, and the tool now suggested a 0x001B001B setting for the MPWLDECTRL1 register.  I then ran the tool again, and a value of 0x001C001C was suggested.  I then ran the tool again, and a calibration of 0x001F001F was suggested (the original value!).  I attempted one final run using the same iterative process and a value of 0x001D001D was suggested.

Please give me an indication of what I might be doing wrong or if I am using the tool incorrectly.

Thanks

Chad Wolter

[Yuri]

Hello,

1.

   In any case, a range of timing parameters may provide proper memory functionality.

This causes different values in calibration results.   

2.

 The following tools may be helpful.

i.MX6ULL_DDR3_Script_Aid 

https://community.nxp.com/docs/DOC-333933 

Regards,

Yuri.

[chadwolter]

Unfortunately, this response just generates more questions; and I don't think my question was fully read or understood before an answer was generated:

You stated (from the DRAM Port Applcation Guide - DDR3): "During the calibration processes, the valid delay window is shown for each calibration (except Write Leveling Calibration).  The delay windows us a rough idea how much timing margin on read DQS, and data setup and hold time for DDR3 read and write operations. In general, the wider the window, the board has more time margin.”

1.  The register I mentioned in my example above IS the write leveling calibration (so a window would not be displayed anyway), further the output of the stress tester gives no ranges for calibration registers that I can see.  I attached the stress tester's output for your review.

2.  The document mentions the script aid, but it appears to be only for i.MX6DQSDL...we are using an i.MX6ULL.  Is there a script available for the ULL?

Please answer quickly as I need to get this done.

thanks

Chad Wolter

OUTPUT of DDR test tool:

============================================
        DDR Stress Test (2.6.0)
        Build: Aug  1 2017, 17:34:06
        NXP Semiconductors.
============================================

============================================
        Chip ID
CHIP ID = i.MX6 UltraLiteLite(0x65)
Internal Revision = TO1.0
============================================

============================================
        Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00004868
SRC_SBMR2(0x020d801c) = 0x01000001
============================================

ARM Clock set to 528MHz

============================================
        DDR configuration
DDR type is DDR3
Data width: 16, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 512MB
============================================

Current Temperature: 39
============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00000000
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001D001D
Write DQS delay result:
   Write DQS0 delay: 0/256 CK
   Write DQS1 delay: 0/256 CK

Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x00000001
. HC_DEL=0x00000001 result[01]=0x00000000
. HC_DEL=0x00000002 result[02]=0x00000000
. HC_DEL=0x00000003 result[03]=0x00000011
. HC_DEL=0x00000004 result[04]=0x00000011
. HC_DEL=0x00000005 result[05]=0x00000011
. HC_DEL=0x00000006 result[06]=0x00000011
. HC_DEL=0x00000007 result[07]=0x00000011
. HC_DEL=0x00000008 result[08]=0x00000011
. HC_DEL=0x00000009 result[09]=0x00000011
. HC_DEL=0x0000000A result[0A]=0x00000011
. HC_DEL=0x0000000B result[0B]=0x00000011
. HC_DEL=0x0000000C result[0C]=0x00000011
. HC_DEL=0x0000000D result[0D]=0x00000011
DQS HC delay value low1 = 0x00000001, high1=0x00000202

loop ABS offset to get HW_DG_LOW
. ABS_OFFSET=0x00000000 result[00]=0x00000001
. ABS_OFFSET=0x00000004 result[01]=0x00000001
. ABS_OFFSET=0x00000008 result[02]=0x00000001
. ABS_OFFSET=0x0000000C result[03]=0x00000001
. ABS_OFFSET=0x00000010 result[04]=0x00000001
. ABS_OFFSET=0x00000014 result[05]=0x00000001
. ABS_OFFSET=0x00000018 result[06]=0x00000000
. ABS_OFFSET=0x0000001C result[07]=0x00000000
. ABS_OFFSET=0x00000020 result[08]=0x00000000
. ABS_OFFSET=0x00000024 result[09]=0x00000000
. ABS_OFFSET=0x00000028 result[0A]=0x00000000
. ABS_OFFSET=0x0000002C result[0B]=0x00000000
. ABS_OFFSET=0x00000030 result[0C]=0x00000000
. ABS_OFFSET=0x00000034 result[0D]=0x00000000
. ABS_OFFSET=0x00000038 result[0E]=0x00000000
. ABS_OFFSET=0x0000003C result[0F]=0x00000000
. ABS_OFFSET=0x00000040 result[10]=0x00000000
. ABS_OFFSET=0x00000044 result[11]=0x00000000
. ABS_OFFSET=0x00000048 result[12]=0x00000000
. ABS_OFFSET=0x0000004C result[13]=0x00000000
. ABS_OFFSET=0x00000050 result[14]=0x00000000
. ABS_OFFSET=0x00000054 result[15]=0x00000000
. ABS_OFFSET=0x00000058 result[16]=0x00000000
. ABS_OFFSET=0x0000005C result[17]=0x00000000
. ABS_OFFSET=0x00000060 result[18]=0x00000000
. ABS_OFFSET=0x00000064 result[19]=0x00000000
. ABS_OFFSET=0x00000068 result[1A]=0x00000000
. ABS_OFFSET=0x0000006C result[1B]=0x00000000
. ABS_OFFSET=0x00000070 result[1C]=0x00000000
. ABS_OFFSET=0x00000074 result[1D]=0x00000000
. ABS_OFFSET=0x00000078 result[1E]=0x00000000
. ABS_OFFSET=0x0000007C result[1F]=0x00000000

loop ABS offset to get HW_DG_HIGH
. ABS_OFFSET=0x00000000 result[00]=0x00000000
. ABS_OFFSET=0x00000004 result[01]=0x00000000
. ABS_OFFSET=0x00000008 result[02]=0x00000000
. ABS_OFFSET=0x0000000C result[03]=0x00000000
. ABS_OFFSET=0x00000010 result[04]=0x00000000
. ABS_OFFSET=0x00000014 result[05]=0x00000000
. ABS_OFFSET=0x00000018 result[06]=0x00000000
. ABS_OFFSET=0x0000001C result[07]=0x00000000
. ABS_OFFSET=0x00000020 result[08]=0x00000000
. ABS_OFFSET=0x00000024 result[09]=0x00000000
. ABS_OFFSET=0x00000028 result[0A]=0x00000000
. ABS_OFFSET=0x0000002C result[0B]=0x00000000
. ABS_OFFSET=0x00000030 result[0C]=0x00000000
. ABS_OFFSET=0x00000034 result[0D]=0x00000000
. ABS_OFFSET=0x00000038 result[0E]=0x00000000
. ABS_OFFSET=0x0000003C result[0F]=0x00000000
. ABS_OFFSET=0x00000040 result[10]=0x00000000
. ABS_OFFSET=0x00000044 result[11]=0x00000000
. ABS_OFFSET=0x00000048 result[12]=0x00000001
. ABS_OFFSET=0x0000004C result[13]=0x00000001
. ABS_OFFSET=0x00000050 result[14]=0x00000011
. ABS_OFFSET=0x00000054 result[15]=0x00000011
. ABS_OFFSET=0x00000058 result[16]=0x00000011
. ABS_OFFSET=0x0000005C result[17]=0x00000011
. ABS_OFFSET=0x00000060 result[18]=0x00000011
. ABS_OFFSET=0x00000064 result[19]=0x00000011
. ABS_OFFSET=0x00000068 result[1A]=0x00000011
. ABS_OFFSET=0x0000006C result[1B]=0x00000011
. ABS_OFFSET=0x00000070 result[1C]=0x00000011
. ABS_OFFSET=0x00000074 result[1D]=0x00000011
. ABS_OFFSET=0x00000078 result[1E]=0x00000011
. ABS_OFFSET=0x0000007C result[1F]=0x00000011

BYTE 0:
 Start:   HC=0x00 ABS=0x18
 End:   HC=0x02 ABS=0x44
 Mean:   HC=0x01 ABS=0x2E
 End-0.5*tCK:  HC=0x01 ABS=0x44
 Final:   HC=0x01 ABS=0x44
BYTE 1:
 Start:   HC=0x00 ABS=0x00
 End:   HC=0x02 ABS=0x4C
 Mean:   HC=0x01 ABS=0x26
 End-0.5*tCK:  HC=0x01 ABS=0x4C
 Final:   HC=0x01 ABS=0x4C

DQS calibration MMDC0 MPDGCTRL0 = 0x414C0144, MPDGCTRL1 = 0x00000000

Note: Array result[] holds the DRAM test result of each byte. 
      0: test pass.  1: test fail 
      4 bits respresent the result of 1 byte.   
      result 01:byte 0 fail.
      result 11:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000 result[00]=0x11
ABS_OFFSET=0x04040404 result[01]=0x01
ABS_OFFSET=0x08080808 result[02]=0x01
ABS_OFFSET=0x0C0C0C0C result[03]=0x00
ABS_OFFSET=0x10101010 result[04]=0x00
ABS_OFFSET=0x14141414 result[05]=0x00
ABS_OFFSET=0x18181818 result[06]=0x00
ABS_OFFSET=0x1C1C1C1C result[07]=0x00
ABS_OFFSET=0x20202020 result[08]=0x00
ABS_OFFSET=0x24242424 result[09]=0x00
ABS_OFFSET=0x28282828 result[0A]=0x00
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00
ABS_OFFSET=0x30303030 result[0C]=0x00
ABS_OFFSET=0x34343434 result[0D]=0x00
ABS_OFFSET=0x38383838 result[0E]=0x00
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00
ABS_OFFSET=0x40404040 result[10]=0x00
ABS_OFFSET=0x44444444 result[11]=0x00
ABS_OFFSET=0x48484848 result[12]=0x00
ABS_OFFSET=0x4C4C4C4C result[13]=0x00
ABS_OFFSET=0x50505050 result[14]=0x00
ABS_OFFSET=0x54545454 result[15]=0x00
ABS_OFFSET=0x58585858 result[16]=0x00
ABS_OFFSET=0x5C5C5C5C result[17]=0x00
ABS_OFFSET=0x60606060 result[18]=0x00
ABS_OFFSET=0x64646464 result[19]=0x10
ABS_OFFSET=0x68686868 result[1A]=0x11
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11
ABS_OFFSET=0x70707070 result[1C]=0x11
ABS_OFFSET=0x74747474 result[1D]=0x11
ABS_OFFSET=0x78787878 result[1E]=0x11
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11

Byte 0: (0x0c - 0x64), middle value:0x38
Byte 1: (0x04 - 0x60), middle value:0x32

MMDC0 MPRDDLCTL = 0x40403238

Starting Write calibration...

ABS_OFFSET=0x00000000 result[00]=0x11
ABS_OFFSET=0x04040404 result[01]=0x11
ABS_OFFSET=0x08080808 result[02]=0x10
ABS_OFFSET=0x0C0C0C0C result[03]=0x00
ABS_OFFSET=0x10101010 result[04]=0x00
ABS_OFFSET=0x14141414 result[05]=0x00
ABS_OFFSET=0x18181818 result[06]=0x00
ABS_OFFSET=0x1C1C1C1C result[07]=0x00
ABS_OFFSET=0x20202020 result[08]=0x00
ABS_OFFSET=0x24242424 result[09]=0x00
ABS_OFFSET=0x28282828 result[0A]=0x00
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00
ABS_OFFSET=0x30303030 result[0C]=0x00
ABS_OFFSET=0x34343434 result[0D]=0x00
ABS_OFFSET=0x38383838 result[0E]=0x00
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00
ABS_OFFSET=0x40404040 result[10]=0x00
ABS_OFFSET=0x44444444 result[11]=0x00
ABS_OFFSET=0x48484848 result[12]=0x00
ABS_OFFSET=0x4C4C4C4C result[13]=0x00
ABS_OFFSET=0x50505050 result[14]=0x00
ABS_OFFSET=0x54545454 result[15]=0x00
ABS_OFFSET=0x58585858 result[16]=0x00
ABS_OFFSET=0x5C5C5C5C result[17]=0x01
ABS_OFFSET=0x60606060 result[18]=0x01
ABS_OFFSET=0x64646464 result[19]=0x01
ABS_OFFSET=0x68686868 result[1A]=0x11
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11
ABS_OFFSET=0x70707070 result[1C]=0x11
ABS_OFFSET=0x74747474 result[1D]=0x11
ABS_OFFSET=0x78787878 result[1E]=0x11
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11

Byte 0: (0x08 - 0x58), middle value:0x30
Byte 1: (0x0c - 0x64), middle value:0x38

MMDC0 MPWRDLCTL = 0x40403830

   MMDC registers updated from calibration

   Write leveling calibration
   MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00000000
   MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001D001D

   Read DQS Gating calibration
   MPDGCTRL0 PHY0 (0x021b083c) = 0x414C0144
   MPDGCTRL1 PHY0 (0x021b0840) = 0x00000000

   Read calibration
   MPRDDLCTL PHY0 (0x021b0848) = 0x40403238

   Write calibration
   MPWRDLCTL PHY0 (0x021b0850) = 0x40403830

Success: DDR calibration completed!!!

[Yuri]

Hello,

  Please refer to the DDR3 Porting Guide how to use the Stress Tool.

Freescale i.MX6 DRAM Port Application Guide-DDR3 

 In particular, according to section 3.3.1 (Identifying Issue on Calibrations) of “i.MX6 DRAM Port Application Guide”:

“During the calibration processes, the valid delay window is shown for each calibration (except Write Leveling Calibration).

The delay windows us a rough idea how much timing margin on read DQS, and data setup and hold time for DDR3 read

and write operations. In general, the wider the window, the board has more time margin.”

  So, really calibration process, depending on board PCB design, provides timing margins, that may change even for the

same board for several test passes. Customers should find optimal solution for all possible environments.

Please look at section 7.3 (Timing Calibrations Usage) of app note AN4467 (i.MX 6 Series DDR Calibration)

https://www.nxp.com/docs/en/application-note/AN4467.pdf 

Have a great day,
Yuri

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[chadwolter]

Hi Yuri –

I responded to the below online. Coincidentally, how do I get my question to appear in the public forum? I am attempting to share this with a colleague, and he can’t see my posts because they are apparently private…

Chad