There seems to be an inconsistency between the iMX6SDL CCM Clock Tree diagram (figure 18-3) and the BUS clock generation (diagram (figure 18-5).
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Hi Michel
1. BUS clock generation (diagram (figure 18-5) is correct. Figure 18-3 is just simplified figure.
2. Yes, correct is PLL2_PFD2 /2.
3. burn_in_bist is used for factory testing only.
Best regards
chip
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Hi Michel
1. BUS clock generation (diagram (figure 18-5) is correct. Figure 18-3 is just simplified figure.
2. Yes, correct is PLL2_PFD2 /2.
3. burn_in_bist is used for factory testing only.
Best regards
chip
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
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