In IMX6ULL, how to use capture1 of GPT2 to capture the external PWM signal

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In IMX6ULL, how to use capture1 of GPT2 to capture the external PWM signal

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rainho
Contributor II

I rewrote a driver with reference to time.c, and the main contents are as follows:

   // get irq
    gpt->irq=platform_get_irq(pdev,0);
    if (gpt->irq<0) {
        dev_err(&pdev->dev, "can't get irq number\n");
        return gpt->irq;
    }

    ret=devm_request_irq(&pdev->dev,gpt->irq,gpt->irq_handler,0,pdev->name,gpt);
    if (ret) {
        dev_err(&pdev->dev, "can't claim irq %d\n", gpt->irq);
        goto exit;
    }

    // get IO
    gpt->gpio_pin=of_get_named_gpio(pdev->dev.of_node,"capture-gpios",0);
    if (!gpio_is_valid(gpt->gpio_pin)) {
        dev_err(&pdev->dev, "invalid GPIO pin\n");
        ret = -EINVAL;
        goto exit;
    }

    ret=devm_gpio_request_one(&pdev->dev,gpt->gpio_pin,GPIOF_DIR_IN,pdev->name);
    if (ret) {
        dev_err(&pdev->dev, "failed to request GPIO pin\n");
        goto exit;
    }

    /*
     * Initialise to a known state (all timers off, and timing reset)
     */
    __raw_writel(V2_TCTL_SWR,gpt->base + MXC_TCTL);
    while(__raw_readl(gpt->base + MXC_TCTL) & V2_TCTL_SWR);

    __raw_writel(0, gpt->base + MXC_TCTL);
    __raw_writel(0, gpt->base + MXC_TPRER); /* see datasheet note */
    dev_info(&pdev->dev,"gpt ipgclk is %ldHZ\r\n",clk_get_rate(gpt->ipg_clk));
    dev_info(&pdev->dev,"gpt perclk is %ldHZ\r\n",clk_get_rate(gpt->per_clk));

    tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_ENMOD |V2_TCTL_WAITEN | V2_TCTL_STOPEN;
    __raw_writel((clk_get_rate(gpt->ipg_clk)/1000000)<<V2_TPRER_PRE,gpt->base + MXC_TPRER); //66 div

    __raw_writel(tctl_val, gpt->base + MXC_TCTL);

    //clear intbit
    __raw_writel(0,gpt->base + V2_SR);
 
 
The device tree is as follows:
&gpt2 {
    compatible = "ainuode,gpt2";
    pinctrl-name = "default";
    pinctrl-0 = <&pinctrl_gpt2cap>;
    reg = <0x020e8000 0x4000>;
    interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&clks IMX6UL_CLK_IPG>,
            <&clks IMX6UL_CLK_GPT2_BUS>;
    clock-names = "ipg", "per";
    capture-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
    status = "okay";
};
 
        pinctrl_gpt2cap: capgrp{
            fsl,pin=<
                MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1   0x1b0b1
            >;
        };
 
There are also some, configuration interrupt enables, input modes, etc., which are also verified to be successful and will not be posted here.

I have checked that the register configuration is correct. I hope you can answer it. Thank you very much and wish you all the best.

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Dhruvit
NXP TechSupport
NXP TechSupport

Hi @rainho 

I hope you are doing well.

I have a few queries to ask.

  • Please cross-check whether the pin control that is defined in the device tree is allocated by the custom driver or not.
  • What output do you get from kernel messages about gpt, Please share the dmesg logs.

Thanks & Regards,
Dhruvit Vasavada

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