Imx8qxp u-boot rmii not working

[mdmosaddekhossa]

U-boot info:

https://source.codeaurora.org/external/imx/uboot-imx.git/

branch -> imx_v2019.04_4.19.35_1.1.0

I am working on a custom board from Imx8qxp. Currently I am facing problem to setup rmii phy of micrel ksz8081rnb. Previously we used mii phy of micrel ksz8081mnx, and we came across the imx8qxp reference manual that it can support from 50MHZ. Thus we changed the phy for rmii. 

Ref_clk generates 50 Mhz and set as an input clk SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN.

Device tree:- 

pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000041
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN 0x00000061

// SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x00000061
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000061
SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x00000021
>;
};

We are using fec1 [enet0] with 50MHz clk.

&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;

clocks = <&clk IMX8QXP_ENET0_IPG_CLK>,
<&clk IMX8QXP_ENET0_AHB_CLK>,
<&clk IMX8QXP_ENET0_RMII_RX_CLK>,
<&clk IMX8QXP_ENET0_PTP_CLK>,
<&clk IMX8QXP_ENET0_TX_CLK>;

assigned-clocks = <&clk IMX8QXP_ENET0_PTP_CLK>,
<&clk IMX8QXP_ENET0_REF_DIV>;
assigned-clock-rates = <50000000>, <50000000>; /*clk changed*/

status = "okay";

phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <150>;

mdio {
#address-cells = <1>;
#size-cells = <0>;

ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
max-speed =<100>;
reg = <1>;
};
};

};

U-boot log:-

clk shows that it has been configured correcly

Mii dump shows all the configuration correct

I have integrated pcap in the u-boot as it was not supported in the u-boot that i am using. To see the packages. Zero packages are sent or received 

Oscilloscope:

I check via oscilloscope the txd0 and txd1 there is no signal. The rxd0,rxd1 have signals.

My Observation:

Note: Is it a hardware issue ? Or is the device tree configuration is not correct?

It will be really helpful if anyone finds a solution or and vital suggestion. 

[mosaddek_hossai]

Dear NXP Community,

If RMII needs to work in IMX8qxp u-boot. First hardware design needs 3.3v. Also there are two magic registers that need to be enabled in Device Tree. After spending a lot of time reading the data sheet of IMX8QXP I have found the there are two magic registers that need to be enabled in device Tree.

pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */

[joanxie]

refer to the RM, In RMII transmit mode, TXD[1:0] provides valid data for each REF_CLK period while
TXEN is asserted. did you test TXEN? the dts file you change is in the kernel, do you need to boot up in the kernel or uboot, if uboot, how did you change in the uboot? I have a document about porting in the uboot on imx7d board, maybe you can refer to it, check if you set correct according to your HW design

https://community.nxp.com/docs/DOC-343802

[mdmosaddekhossa]

Hello Joan Xie,

Thanks for the reply. The configurations are in u-boot. I need the ethernet running in my u-boot first. 

The dts file is from my u-boot. I have used the device tree to configure my ethernet phy and fec. 

The driver config files are also similar according to your refeence link https://community.nxp.com/docs/DOC-343802.

I am using micrel ksz8081rnb phy for rmii. I am rechecking the HW design and REF_CLK period while TXEN is asserted.

Defconfig for fec , phy and cmd tools:

CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y

CONFIG_PHY_MICREL=y
# CONFIG_PHY_MICREL_KSZ90X1 is not set
CONFIG_PHY_MICREL_KSZ8XXX=y

CONFIG_PHY_FIXED=y

CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y

CONFIG_ETHOC=y
CONFIG_FEC_MXC_SHARE_MDIO=y
CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
CONFIG_FEC_MXC=y

CONFIG_MII=y
CONFIG_RMII=y

#
# Shell scripting commands
#
CONFIG_CMD_ECHO=y
CONFIG_CMD_ITEST=y
CONFIG_CMD_SOURCE=y
CONFIG_CMD_SETEXPR=y
CONFIG_CMD_NET=y
CONFIG_CMD_BOOTP=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_DNS=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
CONFIG_BOOTP_SUBNETMASK=y
CONFIG_CMD_TFTPBOOT=y
CONFIG_NET_TFTP_VARS=y
CONFIG_CMD_NFS=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DNS=y
CONFIG_CMD_LINK_LOCAL=y
CONFIG_CMD_PCAP=y

board.h file:

/******************************************************************************************************/
/****************************** Networking config*************************************/
/******************************************************************************************************/

#define CONFIG_FEC_XCV_TYPE RMII
#define FEC_QUIRK_ENET_MAC

#define CONFIG_FEC_ENET_DEV 0
#if (CONFIG_FEC_ENET_DEV == 0)
#define IMX_FEC_BASE 0x5B040000
#define CONFIG_FEC_MXC_PHYADDR 0x01
#define CONFIG_ETHPRIME "eth0"
#endif

//#define CONFIG_PHY_MICREL

#ifndef CONFIG_LIB_RAND
#define CONFIG_LIB_RAND
#endif
//#define CONFIG_NET_RANDOM_ETHADDR
#define CONFIG_IP_DEFRAG
#define CONFIG_TFTP_BLOCKSIZE SZ_4K
#define CONFIG_TFTP_TSIZE
#define CONFIG_SERVERIP 10.0.0.1

I have also used the link as reference

The board phy_config in my board.c file:

int board_phy_config(struct phy_device *phydev)
{
//phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);

if (phydev->drv->config)
phydev->drv->config(phydev);

return 0;
}

[mdmosaddekhossa]

Hallo Jaon Xie,

Also there is no signal in TXEN. Does it mean there is problem in MAC configuration. Because my phy is looking good.

[joanxie]

did you check your HW connection? pls be sure if your HW connection is ok

[mdmosaddekhossa]

We have found that there is a hardware issue, the rmii needs 3.3v from the chip to start communication. Our board design need to be changed for RMII phy.