Imx6ull SAI1_MCLK is not present

sergio_dorazio · ‎11-05-2019

Hi,

I am connecting the codec audio to SAI1 device but after correct configuration the MCLK signal isn't present.

In a forum I read that I must change in .dts file this row : gpr = <&gpr 4 0x100000 0x100000>;

Can you send me the correction for MCLK from SAI1 ?

Sergio.

weidong_sun · ‎11-05-2019

Hi sergio,

If you want to use SAI1_MCLK, you will change the flowing items in device tree:

------------------------------

IOMUXC_GPR_GPR1
    sound {
        compatible = "fsl,imx6ul-evk-wm8960",
               "fsl,imx-audio-wm8960";
        model = "wm8960-audio";
        cpu-dai = <&sai2>;
        audio-codec = <&codec>;
        asrc-controller = <&asrc>;
        codec-master;
        gpr = <&gpr 4 0x80000 0x80000>;   // see IOMUXC_GPR_GPR1 register in reference manual. bit19 should be 1.
        /*
                 * hp-det = <hp-det-pin hp-det-polarity>;
        * hp-det-pin: JD1 JD2 or JD3
        * hp-det-polarity = 0: hp detect high for headphone
        * hp-det-polarity = 1: hp detect high for speaker
        */
        hp-det = <3 0>;

......
}

// change these pins for yours
    pinctrl_sai2: sai2grp {
        fsl,pins = <
            MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK    0x17088
            MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC    0x17088
            MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA    0x11088
            MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA    0x11088
            MX6UL_PAD_JTAG_TMS__SAI2_MCLK        0x17088
        >;
    };
// // change the driver for sai1

&sai2 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sai2
             &pinctrl_sai2_hp_det_b>;

    assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
            <&clks IMX6UL_CLK_SAI2>;
    assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
    assigned-clock-rates = <0>, <12288000>;

    status = "okay";
};

------------------------------------------------

Try it , please!

BR,

Weidong

View solution in original post

weidong_sun · ‎11-05-2019

Hi sergio,

If you want to use SAI1_MCLK, you will change the flowing items in device tree:

------------------------------

IOMUXC_GPR_GPR1
    sound {
        compatible = "fsl,imx6ul-evk-wm8960",
               "fsl,imx-audio-wm8960";
        model = "wm8960-audio";
        cpu-dai = <&sai2>;
        audio-codec = <&codec>;
        asrc-controller = <&asrc>;
        codec-master;
        gpr = <&gpr 4 0x80000 0x80000>;   // see IOMUXC_GPR_GPR1 register in reference manual. bit19 should be 1.
        /*
                 * hp-det = <hp-det-pin hp-det-polarity>;
        * hp-det-pin: JD1 JD2 or JD3
        * hp-det-polarity = 0: hp detect high for headphone
        * hp-det-polarity = 1: hp detect high for speaker
        */
        hp-det = <3 0>;

......
}

// change these pins for yours
    pinctrl_sai2: sai2grp {
        fsl,pins = <
            MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK    0x17088
            MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC    0x17088
            MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA    0x11088
            MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA    0x11088
            MX6UL_PAD_JTAG_TMS__SAI2_MCLK        0x17088
        >;
    };
// // change the driver for sai1

&sai2 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sai2
             &pinctrl_sai2_hp_det_b>;

    assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
            <&clks IMX6UL_CLK_SAI2>;
    assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
    assigned-clock-rates = <0>, <12288000>;

    status = "okay";
};

------------------------------------------------

Try it , please!

BR,

Weidong

sergio_dorazio · ‎11-06-2019

Hi Sun,

thank you for your suggestion. Now MCLK is present but the audio card is not seen.

I send you my .dts file :

/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/

/dts-v1/;

#include <dt-bindings/input/input.h>
#include "imx6ull.dtsi"

/ {
model = "Freescale i.MX6 ULL 14x14 EVK Board";
compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";

   chosen {
       stdout-path = &uart1;
   };

   memory {
       reg = <0x80000000 0x10000000>;
   };

   reserved-memory {
       #address-cells = <1>;
       #size-cells = <1>;
       ranges;

       linux,cma {
           compatible = "shared-dma-pool";
           reusable;
           size = <0xC000000>;
           linux,cma-default;
       };
   };
/*
   backlight {
       compatible = "pwm-backlight";
       pwms = <&pwm1 0 5000000>;
       brightness-levels = <0 4 8 16 32 64 128 255>;
       default-brightness-level = <6>;
       status = "okay";
   };
*/
   pxp_v4l2 {
       compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
       status = "okay";
   };

   regulators {
       compatible = "simple-bus";
       #address-cells = <1>;
       #size-cells = <0>;

       reg_can_3v3: regulator@0 {
           compatible = "regulator-fixed";
           reg = <0>;
           regulator-name = "can-3v3";
           regulator-min-microvolt = <3300000>;
           regulator-max-microvolt = <3300000>;
           gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
       };
/*
       reg_sd1_vmmc: regulator@1 {
           compatible = "regulator-fixed";
           regulator-name = "VSD_3V3";
           regulator-min-microvolt = <3300000>;
           regulator-max-microvolt = <3300000>;
           gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
           off-on-delay = <20000>;
           enable-active-high;
       };

       reg_gpio_dvfs: regulator-gpio {
           compatible = "regulator-gpio";
           pinctrl-names = "default";
           pinctrl-0 = <&pinctrl_dvfs>;
           regulator-min-microvolt = <1300000>;
           regulator-max-microvolt = <1400000>;
           regulator-name = "gpio_dvfs";
           regulator-type = "voltage";
           gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
           states = <1300000 0x1 1400000 0x0>;
       };
*/
   };

   sound {
       compatible = "fsl,imx6ul-evk-wm8960",
               "fsl,imx-audio-wm8960";
       model = "wm8960-audio";
       cpu-dai = <&sai1>;
       audio-codec = <&codec>;
       asrc-controller = <&asrc>;
       codec-master;
       gpr = <&gpr 4 0x80000 0x80000>;
       /*
                 * hp-det = <hp-det-pin hp-det-polarity>;
       * hp-det-pin: JD1 JD2 or JD3
       * hp-det-polarity = 0: hp detect high for headphone
       * hp-det-polarity = 1: hp detect high for speaker
       */
       hp-det = <3 0>;
       hp-det-gpios = <&gpio5 4 0>;
       mic-det-gpios = <&gpio5 4 0>;
       audio-routing =
           "Headphone Jack", "HP_L",
           "Headphone Jack", "HP_R",
           "Ext Spk", "SPK_LP",
           "Ext Spk", "SPK_LN",
           "Ext Spk", "SPK_RP",
           "Ext Spk", "SPK_RN",
           "LINPUT2", "Mic Jack",
           "LINPUT3", "Mic Jack",
           "RINPUT1", "Main MIC",
           "RINPUT2", "Main MIC",
           "Mic Jack", "MICB",
           "Main MIC", "MICB",
           "CPU-Playback", "ASRC-Playback",
           "Playback", "CPU-Playback",
           "ASRC-Capture", "CPU-Capture",
           "CPU-Capture", "Capture";
   };

   spi4 {
       compatible = "spi-gpio";
       pinctrl-names = "default";
       pinctrl-0 = <&pinctrl_spi4>;
       pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
       status = "okay";
       gpio-sck = <&gpio5 11 0>;
       gpio-mosi = <&gpio5 10 0>;
       cs-gpios = <&gpio5 7 0>;
       num-chipselects = <1>;
       #address-cells = <1>;
       #size-cells = <0>;

       gpio_spi: gpio_spi@0 {
           compatible = "fairchild,74hc595";
           gpio-controller;
           #gpio-cells = <2>;
           reg = <0>;
           registers-number = <1>;
           registers-default = /bits/ 8 <0x57>;
           spi-max-frequency = <100000>;
       };
   };
};

&cpu0 {
/* dc-supply = <&reg_gpio_dvfs>;*/
};

&clks {
   assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
   assigned-clock-rates = <786432000>;
};
/*
&csi {
   status = "okay";

   port {
       csi1_ep: endpoint {
           remote-endpoint = <&ov5640_ep>;
       };
   };
};
*/
&fec1 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_enet1>;
   phy-mode = "rmii";
   phy-handle = <&ethphy0>;
   status = "okay";
};

&fec2 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_enet2>;
   phy-mode = "rmii";
   phy-handle = <&ethphy1>;
   status = "okay";

   mdio {
       #address-cells = <1>;
       #size-cells = <0>;

       ethphy0: ethernet-phy@2 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <2>;
           micrel,led-mode = <1>;
           clocks = <&clks IMX6UL_CLK_ENET_REF>;
           clock-names = "rmii-ref";
       };

       ethphy1: ethernet-phy@1 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <1>;
           micrel,led-mode = <1>;
           clocks = <&clks IMX6UL_CLK_ENET2_REF>;
           clock-names = "rmii-ref";
       };
   };
};

&flexcan1 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_flexcan1>;
   xceiver-supply = <&reg_can_3v3>;
   status = "okay";
};

&flexcan2 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_flexcan2>;
   xceiver-supply = <&reg_can_3v3>;
   status = "okay";
};

&gpc {
   fsl,cpu_pupscr_sw2iso = <0xf>;
   fsl,cpu_pupscr_sw = <0x0>;
   fsl,cpu_pdnscr_iso2sw = <0x1>;
   fsl,cpu_pdnscr_iso = <0x1>;
   fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
};

&i2c1 {
   clock-frequency = <100000>;
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_i2c1>;
   status = "okay";

   mag3110@0e {
       compatible = "fsl,mag3110";
       reg = <0x0e>;
       position = <2>;
   };

   fxls8471@1e {
       compatible = "fsl,fxls8471";
       reg = <0x1e>;
       position = <0>;
       interrupt-parent = <&gpio5>;
       interrupts = <0 8>;
   };
};

&i2c2 {
   clock_frequency = <100000>;
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_i2c2>;
   status = "okay";

   codec: wm8960@1a {
       compatible = "wlf,wm8960";
       reg = <0x1a>;
       clocks = <&clks IMX6UL_CLK_SAI1>;
       clock-names = "mclk";
       wlf,shared-lrclk;
   };
/*
   ov5640: ov5640@3c {
       compatible = "ovti,ov5640";
       reg = <0x3c>;
       pinctrl-names = "default";
       pinctrl-0 = <&pinctrl_csi1>;
       clocks = <&clks IMX6UL_CLK_CSI>;
       clock-names = "csi_mclk";
       pwn-gpios = <&gpio_spi 6 1>;
       rst-gpios = <&gpio_spi 5 0>;
       csi_id = <0>;
       mclk = <24000000>;
       mclk_source = <0>;
       status = "okay";
       port {
           ov5640_ep: endpoint {
               remote-endpoint = <&csi1_ep>;
           };
       };
   };
*/
};

&iomuxc {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_hog_1>;
   pinctrl_hog_1: hoggrp-1 {
       fsl,pins = <
           MX6UL_PAD_UART1_RTS_B__GPIO1_IO19   0x17059 /* SD1 CD */
           MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT   0x17059 /* SD1 VSELECT */
               MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
       >;
   };
/*
   pinctrl_csi1: csi1grp {
       fsl,pins = <
           MX6UL_PAD_CSI_MCLK__CSI_MCLK       0x1b088
           MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK   0x1b088
           MX6UL_PAD_CSI_VSYNC__CSI_VSYNC       0x1b088
           MX6UL_PAD_CSI_HSYNC__CSI_HSYNC       0x1b088
           MX6UL_PAD_CSI_DATA00__CSI_DATA02   0x1b088
           MX6UL_PAD_CSI_DATA01__CSI_DATA03   0x1b088
           MX6UL_PAD_CSI_DATA02__CSI_DATA04   0x1b088
           MX6UL_PAD_CSI_DATA03__CSI_DATA05   0x1b088
           MX6UL_PAD_CSI_DATA04__CSI_DATA06   0x1b088
           MX6UL_PAD_CSI_DATA05__CSI_DATA07   0x1b088
           MX6UL_PAD_CSI_DATA06__CSI_DATA08   0x1b088
           MX6UL_PAD_CSI_DATA07__CSI_DATA09   0x1b088
       >;
   };
*/
   pinctrl_enet1: enet1grp {
       fsl,pins = <
           MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN   0x1b0b0
           MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER   0x1b0b0
           MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00   0x1b0b0
           MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01   0x1b0b0
           MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN   0x1b0b0
           MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00   0x1b0b0
           MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01   0x1b0b0
           MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1   0x4001b031
       >;
   };

   pinctrl_enet2: enet2grp {
       fsl,pins = <
           MX6UL_PAD_GPIO1_IO07__ENET2_MDC       0x1b0b0
           MX6UL_PAD_GPIO1_IO06__ENET2_MDIO   0x1b0b0
           MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN   0x1b0b0
           MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER   0x1b0b0
           MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00   0x1b0b0
           MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01   0x1b0b0
           MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN   0x1b0b0
           MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00   0x1b0b0
           MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01   0x1b0b0
           MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2   0x4001b031
       >;
   };

   pinctrl_flexcan1: flexcan1grp{
       fsl,pins = <
           MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX   0x1b020
           MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX   0x1b020
       >;
   };

   pinctrl_flexcan2: flexcan2grp{
       fsl,pins = <
           MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX   0x1b020
           MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX   0x1b020
       >;
   };

   pinctrl_i2c1: i2c1grp {
       fsl,pins = <
           MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
           MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
       >;
   };

   pinctrl_i2c2: i2c2grp {
       fsl,pins = <
           MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
           MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
       >;
   };

   pinctrl_pwm1: pwm1grp {
       fsl,pins = <
           MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
       >;
   };

   pinctrl_qspi: qspigrp {
       fsl,pins = <
           MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
           MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
           MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
           MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
           MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
           MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
       >;
   };

   pinctrl_sai1: sai1grp {
       fsl,pins = <
           MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK   0x17088
           MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC   0x17088
           MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA   0x11088
           MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA   0x11088
           MX6UL_PAD_CSI_DATA01__SAI1_MCLK       0x17088
       >;
   };

   pinctrl_tsc: tscgrp {
       fsl,pins = <
           MX6UL_PAD_GPIO1_IO01__GPIO1_IO01   0xb0
           MX6UL_PAD_GPIO1_IO02__GPIO1_IO02   0xb0
           MX6UL_PAD_GPIO1_IO03__GPIO1_IO03   0xb0
           MX6UL_PAD_GPIO1_IO04__GPIO1_IO04   0xb0
       >;
   };

   pinctrl_uart1: uart1grp {
       fsl,pins = <
           MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
           MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
       >;
   };

   pinctrl_uart2: uart2grp {
       fsl,pins = <
           MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
           MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
           MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS   0x1b0b1
           MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS   0x1b0b1
       >;
   };

   pinctrl_uart2dte: uart2dtegrp {
       fsl,pins = <
           MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1
           MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1
           MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS   0x1b0b1
           MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS   0x1b0b1
       >;
   };

   pinctrl_usb_otg1_id: usbotg1idgrp {
       fsl,pins = <
           MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID   0x17059
       >;
   };
/*
   pinctrl_usdhc1: usdhc1grp {
       fsl,pins = <
           MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
           MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10071
           MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
           MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
           MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
           MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
       >;
   };

   pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
       fsl,pins = <
           MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
           MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
           MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
           MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
           MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
           MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
       >;
   };

   pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
       fsl,pins = <
           MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
           MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
           MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
           MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
           MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
           MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
       >;
   };

   pinctrl_usdhc2: usdhc2grp {
       fsl,pins = <
           MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
           MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
           MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
           MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
           MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
           MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
       >;
   };

   pinctrl_usdhc2_8bit: usdhc2grp_8bit {
       fsl,pins = <
           MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
           MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
           MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
           MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
           MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
           MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
           MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
           MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
           MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
           MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
       >;
   };

   pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
       fsl,pins = <
           MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
           MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
           MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
           MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
           MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
           MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
           MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
           MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
           MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
           MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
       >;
   };

   pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
       fsl,pins = <
           MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
           MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
           MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
           MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
           MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
           MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
           MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
           MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
           MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
           MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
       >;
   };
*/
   pinctrl_wdog: wdoggrp {
       fsl,pins = <
           MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
       >;
   };
};

&iomuxc_snvs {
   pinctrl-names = "default_snvs";
        pinctrl-0 = <&pinctrl_hog_2>;
        imx6ul-evk {
       pinctrl_hog_2: hoggrp-2 {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
                        >;
                };

       pinctrl_dvfs: dvfsgrp {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
                        >;
                };

       pinctrl_spi4: spi4grp {
                        fsl,pins = <
                                MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10        0x70a1
                                MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11        0x70a1
                                MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x70a1
                                MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x80000000
                        >;
                };

                pinctrl_sai1_hp_det_b: sai1_hp_det_grp {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04   0x17059
                        >;
                };
        };
};

&pwm1 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_pwm1>;
   status = "okay";
};

&pxp {
status = "okay";
};

&qspi {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_qspi>;
   status = "okay";
   ddrsmp=<0>;

   flash: mt25ql02g@0 {
       compatible = "micron,mt25ql02g";
       #address-cells = <1>;
       #size-cells = <1>;
       spi-max-frequency = <29000000>;
       #spi-nor,ddr-quad-read-dummy = <6>;
       reg = <0>;

       partition@0 {
           label = "uboot";
           reg = <0x000000 0x110000>;
       };

       partition@110000 {
           label = "kernel";
           reg = <0x110000 0x7F0000>;
       };

       partition@900000 {
           label = "dtb";
           reg = <0x900000 0x100000>;
       };

       partition@A00000 {
           label = "user";
           reg = <0xA00000 0xF600000>;
       };

};
};

&sai1 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_sai1
             &pinctrl_sai1_hp_det_b>;

   assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
              <&clks IMX6UL_CLK_SAI1>;
   assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
   assigned-clock-rates = <0>, <12288000>;

status = "okay";
};

&tsc {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_tsc>;
   xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
   measure-delay-time = <0xffff>;
   pre-charge-time = <0xfff>;
   status = "okay";
};

&uart1 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_uart1>;
   status = "okay";
};

&uart2 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_uart2>;
   fsl,uart-has-rtscts;
   /* for DTE mode, add below change */
   /* fsl,dte-mode; */
   /* pinctrl-0 = <&pinctrl_uart2dte>; */
   status = "okay";
};

&usbotg1 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_usb_otg1_id>;
   dr_mode = "otg";
   srp-disable;
   hnp-disable;
   adp-disable;
   status = "okay";
};

&usbotg2 {
   dr_mode = "host";
   disable-over-current;
   status = "okay";
};

&usbphy1 {
fsl,tx-d-cal = <106>;
};

&usbphy2 {
   fsl,tx-d-cal = <106>;
};
/*
&usdhc1 {
   pinctrl-names = "default", "state_100mhz", "state_200mhz";
   pinctrl-0 = <&pinctrl_usdhc1>;
   pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
   pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
   cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
   keep-power-in-suspend;
   enable-sdio-wakeup;
   vmmc-supply = <&reg_sd1_vmmc>;
   status = "okay";
};

&usdhc2 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_usdhc2>;
   non-removable;
   status = "okay";
};
*/
&wdog1 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_wdog>;
   fsl,ext-reset-output;
};

If I do :

~# parecord file.wav

fsl-sai 2028000.sai: ASoC: can't open platform 2028000.sai: -6

if I do :

~# pactl list cards

no cards present

If I do the alsactl restore command I receive error code -11:

:~# alsactl restore -debug
alsactl: set_controls:1479: device='hw:0', doit=0
alsactl: set_controls:1491: card-info-id: 'wm8960audio'
alsactl: set_controls:1517: maxnumid=58
alsactl: set_controls:1528: more controls than maxnumid?
alsactl: set_controls:1535: result code: -11
alsactl: sysfs_init:43: sysfs_path='/sys'

Have you found any errors in my .dts file ?

Have you other suggestion for resolve my errors ?

Sergio.

weidong_sun · ‎11-06-2019

Hi,

Your sound card was not loaded successfully, you should check why.

I didn't find issues from your device tree.

If your audio codec is also wm8960, Then a better way to do this is to add trace code to imx-wm8960. C to confirm that there was an error loading the driver. At the same time, you should also check whether I2C has found wm8960 codec.

Hope above advice is helpful for you.

Have a nice day!

BR,

Weidong