joanxie
Hi Joan Xie,
Same kind of question from me.
I have 1920x720 LVDS panel and add "split-mode" in dtsi of i.mx6.
LVDS panel says: 1920x720 @ 60 = 47.5 Mhz.
Is any limitation of split-mode (odd/even) with resolution on IMX6?
Can you explain IPU DI0 clock settings and LVDS CH0/CH1 serialize clock settings for split-mode ?
The below settings is not functional:
- IPU1 DI0 clock = 47.5 MHz, LDB CH0 serialzer clock = 166 MHz.
- Screen is not synchronized to full 1920x720 panel
//// ** Not functional *** /////
&ldb {
status = "okay";
split-mode;
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
primary;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: C123HAN021 {
clock-frequency = <47500000>;
hactive = <1920>;
vactive = <720>;
hback-porch = <20>;
hfront-porch = <40>;
vback-porch = <20>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;
};
};
};
};
The below settings functional but with limitation
- Screen synchronized to full 1920x720
- But 1/3 portion of screen's color is not proper RGB
- 2/3 portion of screen is proper RGB
- IPU1 DI0 clock = 142.5 MHz, LDB (CH0 serialzer clock) = 498 MHz.
//// ** functional with color limitation*** /////
&ldb {
status = "okay";
split-mode;
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
primary;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: C123HAN021 {
clock-frequency = <142500000>;
hactive = <1920>;
vactive = <720>;
hback-porch = <20>;
hfront-porch = <40>;
vback-porch = <20>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;
};
};
};
};
Please help us to resolve this.
-Ankit.