Imx6 ESAI TX FIFO empty interrupt - is it possible?
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Hello!
Is it possible to generate an interrupt when ESAI TX FIFO gets empty without sdma system usage?
As far as I understand from documentation - TX FIFO Empty event can only trigger an sdma request and it looks like I should write special sdma script to issue an interrupt (interrupt 34?)
May be it is possible to generate an interrupt somehow without using an sdma system?
Thanks!
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Hi sergeydanilov
you are right, TX FIFO Empty event may be generated only with sdma.
Best regards
igor
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Thanks!
could you please clear up this info from the manual (signed with bold):
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25.6.9 Transmit Data Register n (ESAI_TXn)
ESAI_TX5, ESAI_TX4, ESAI_TX3, ESAI_TX2, ESAI_TX1 and ESAI_TX0 are 32-bit
write-only registers. Data to be transmitted is written into these registers and is
automatically transferred to the transmit shift registers (Figure 25-2 and Figure 25-3).
The data written (8, 12, 16, 20, or 24 bits) should occupy the most significant portion of
the TXn according to the ALC control bit setting. The unused bits (least significant
portion and the 8 most significant bits when ALC=1) of the TXn are don't care bits. The
Core is interrupted whenever the TXn becomes empty if the transmit data register empty
interrupt has been enabled.
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The question is - what does the sentence "TXn becomes empty" exactly mean? No more data in TX FIFO to fill up this transmit data register? Or interrupt issued just every time when every enabled transmitter actually transmits data?
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this means that at least one of the enabled transmit data registers is empty (TDE=1),
check Figure 25-1. ESAI Block Diagram, sect.25.4.2 ESAI Interrupt Requests
~igor