Identification of i.MX53 Silicon Revision

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Identification of i.MX53 Silicon Revision

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MOW
Contributor IV

Hi all

I am currently wondering about identification of different i.MX53 silicon revisions in software:

Linux-Kernels seem to read the IIM_SREV register, which seems to contain just some kind of incrementing(?) number for different silicon revisions, with the following known relationships between the IIM_SREV contents and known silicon revisions:

case 0x0: return IMX_CHIP_REVISION_1_0;

case 0x2: return IMX_CHIP_REVISION_2_0;

case 0x3: return IMX_CHIP_REVISION_2_1;

default: return IMX_CHIP_REVISION_UNKNOWN;

I can't find no official documentation on these numbers, though.

All boot-loaders (U-Boot, Barebox, RedBoot) seem to read a byte-constant from the on-chip ROM (offset 0x48) instead, which seems to contain major silicon revision in the high-nibble, and minor silicon revision in the low-nibble, i.e. 0x21 for Revision 2.1. This mechanism seems to be completely undocumented, though.

All fine and dandy, so far: All i.MX53 SoCs (product marking MCIMX535DVV1C N78C) we equipped in our products so far returned 0x3 via IIM_SREV and 0x21 via the ROM-constant. Just recently we noticed i.MX535 SoCs (identical product marking on the chip), which return 0x4 in IIM_SREV instead and therefore are not properly recognized by the Linux kernel anymore, but still return 0x21 (i.e. Rev 2.1) in the ROM-constant read by the bootloaders.

What happened with these newer(?) SoCs? Which way is the proper way to identify i.MX53 silicon revisions in software? Is there any official documentation available on this?

Kind regards,

Marc

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Yuri
NXP TechSupport
NXP TechSupport

Hello, Marc !

  You are right, basically there are two ways to accomplish identifying the
revision of the i.MX53:

1) Fuse map ; IIM_SREV :
  TO1    = 0 ;
  TO2 = 2 ;

  TO2.1 = 3 ; (mask N78C)

  TO2.1 =  4. (mask 3N78C)

2) The silicon revision is stored in the ROM code at absolute physical
address 0x48 :
  TO1   = 0x10;

   TO2   = 0x20 ;
   TO2.1 = 0x21.

 

  As for mask 3N78C :

http://cache.freescale.com/files/shared/doc/pcn/PCN15924.htm


Have a great day,
Yuri

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MOW
Contributor IV

Hello Yuri

Thanks for the clarification. So both N78C (IIM_SREV = 0x3) and 3N78C (IIM_SREV = 0x4) are considered as silicon revision TO2.1, which the current datasheets refer to?

I am still somewhat puzzled, though: The PCN you linked states that 3N78C should also be marked as "3N78C" on the chip-package, but ours aren't: I currently have on system right in front of me with the following chip-markings: "MCIMX535DVV1C  N78C  SBAN14390  KOREA", i.e. definitely no 3N78C but it still returns 0x4 in IIM_SREV.

And why does the Freescale's i.MX53 Linux kernel use the IIM_SREV register, but implements just an incomplete mapping from IIM_SREV-contents to TO-revisions?

Kind regards,

Marc

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