I'm having some trouble understanding the right register to set the QoS priority for the IPUs, as the manual makes it seem like there are two different places (references are to the Quad Plus manual here.)
There's IOMUXC_GPR6 and GPR7 (section 36.4.7-8) which control IPU1 R/W AXI ID QoS priorities.
Then there's the AQoS control registers associated with the IPUs (section 47.3. Actually here the manual lists the IPUs as IPU0 and IPU1, but I'm assuming they meant 1 and 2.) These contain a priority register. The field description is:
P0: In Regulator mode, defines the LOW hurry level. In Fixed/Limiter mode, defines the Urgency level for WRITE transactions.
P1: In Regulator mode, defines the HIGH hurry level. In Fixed/Limiter mode, defines the Urgency level for READ transactions.
So I'm wondering what the difference between the GPR6/7 registers and the AQoS priority registers are. I'm not super experienced with embedded systems, so apologies if the answer is obvious. Thanks for the help!
Hi Kirsten
in general there is no difference between these two descriptions, prefered and
more convenient option to use IOMUXC_GPR6 and GPR7 registers.
Best regards
igor
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Thanks for the reply! How does the coordination between these two places work, if only GPR6 and GPR7 need to be set? In our application, we store a certain setting in GPR6 and GPR7, but probing the AQoS registers for the IPUs, I can see they hold different values. That seems a little suspicious to me if both places are interchangeable, since I would maybe expect the setting to get copied over automatically. Am I missing something?
Hi Kirsten
IPU Chapter of Reference Manual gives generic module IP description,
which is used in many i.MX processors. Specific i.MX6Q implementation has
IOMUXC_GPR6 and GPR7 registers for convenience of programming. Recommended
to use them.
Best regards
igor