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IPU IC on iMX6Q Plus

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IPU IC on iMX6Q Plus

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‎01-27-2023 04:48 AM
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ensc
Contributor III

I try to use the IPU IC to convert images in the post-processor (fmem channel 11 -> fmem channel 22).

Things work as expected on an iMX6Q but operation is stuck on iMX6QPlus.

A simple reproducer on Linux (Kernel 6.1) is

gst-launch-1.0 videotestsrc num-buffers=1 \! \
    "video/x-raw,format=NV12,width=256,height=128" \! \
    v4l2convert \! "video/x-raw,width=128" \! \
    filesink location=/tmp/a

 It finishes on iMX6Q but hangs on iMX6QPlus.  It uses the

| # v4l2-ctl -d /dev/video8 --all
| Driver Info:
|         Driver name      : imx-csc-scaler
|         Card type        : imx-csc-scaler
|         Bus info         : platform:imx-csc-scaler

device.

iMX6QPlus has a new prefetcher unit but afais, it is related to the display related dma channels.  What has been changed else resp. what must be done to use the IC again?

 

More examples:  after

 

 

strace output

ioctl(6, VIDIOC_QUERYCAP, {driver="imx-csc-scaler", card="imx-csc-scaler", bus_info="platform:imx-csc-scaler", version=KERNEL_VERSION(6, 1, 8), capabilities=V4L2_CAP_VIDEO_M2M|V4L2_CAP_EXT_PIX_FORMAT|V4L2_CAP_STREAMING|V4L2_CAP_DEVICE_CAPS, device_caps=V4L2_CAP_VIDEO_M2M|V4L2_CAP_EXT_PIX_FORMAT|V4L2_CAP_STREAMING}) = 0
ioctl(6, VIDIOC_G_FMT, {type=V4L2_BUF_TYPE_VIDEO_CAPTURE, fmt.pix={width=720, height=576, pixelformat=v4l2_fourcc('Y', 'U', '1', '2') /* V4L2_PIX_FMT_YUV420 */, field=V4L2_FIELD_NONE, bytesperline=720, sizeimage=622080, colorspace=V4L2_COLORSPACE_SRGB}}) = 0
ioctl(6, VIDIOC_G_FMT, {type=V4L2_BUF_TYPE_VIDEO_OUTPUT, fmt.pix={width=720, height=576, pixelformat=v4l2_fourcc('Y', 'U', '1', '2') /* V4L2_PIX_FMT_YUV420 */, field=V4L2_FIELD_NONE, bytesperline=720, sizeimage=622080, colorspace=V4L2_COLORSPACE_SRGB}}) = 0
ioctl(6, VIDIOC_S_FMT, {type=V4L2_BUF_TYPE_VIDEO_OUTPUT, fmt.pix={width=128, height=128, pixelformat=v4l2_fourcc('Y', 'U', 'Y', 'V') /* V4L2_PIX_FMT_YUYV */, field=V4L2_FIELD_ANY, bytesperline=0, sizeimage=0, colorspace=V4L2_COLORSPACE_DEFAULT}} => {fmt.pix={width=128, height=128, pixelformat=v4l2_fourcc('Y', 'U', 'Y', 'V') /* V4L2_PIX_FMT_YUYV */, field=V4L2_FIELD_NONE, bytesperline=256, sizeimage=32768, colorspace=V4L2_COLORSPACE_SRGB}}) = 0
ioctl(6, VIDIOC_G_FMT, {type=V4L2_BUF_TYPE_VIDEO_OUTPUT, fmt.pix={width=128, height=128, pixelformat=v4l2_fourcc('Y', 'U', 'Y', 'V') /* V4L2_PIX_FMT_YUYV */, field=V4L2_FIELD_NONE, bytesperline=256, sizeimage=32768, colorspace=V4L2_COLORSPACE_SRGB}}) = 0
ioctl(6, VIDIOC_REQBUFS, {type=V4L2_BUF_TYPE_VIDEO_OUTPUT, memory=V4L2_MEMORY_MMAP, count=3 => 3}) = 0
ioctl(6, VIDIOC_QUERYBUF_TIME32, {type=V4L2_BUF_TYPE_VIDEO_OUTPUT, index=0, memory=V4L2_MEMORY_MMAP, m.offset=0, length=32768, flags=V4L2_BUF_FLAG_TIMESTAMP_COPY|V4L2_BUF_FLAG_TSTAMP_SRC_EOF, ...}) = 0
ioctl(6, VIDIOC_QUERYBUF_TIME32, {type=V4L2_BUF_TYPE_VIDEO_OUTPUT, index=1, memory=V4L2_MEMORY_MMAP, m.offset=0x8000, length=32768, flags=V4L2_BUF_FLAG_TIMESTAMP_COPY|V4L2_BUF_FLAG_TSTAMP_SRC_EOF, ...}) = 0
ioctl(6, VIDIOC_QUERYBUF_TIME32, {type=V4L2_BUF_TYPE_VIDEO_OUTPUT, index=2, memory=V4L2_MEMORY_MMAP, m.offset=0x10000, length=32768, flags=V4L2_BUF_FLAG_TIMESTAMP_COPY|V4L2_BUF_FLAG_TSTAMP_SRC_EOF, ...}) = 0
ioctl(6, VIDIOC_S_FMT, {type=V4L2_BUF_TYPE_VIDEO_CAPTURE, fmt.pix={width=128, height=128, pixelformat=v4l2_fourcc('Y', 'U', 'Y', 'V') /* V4L2_PIX_FMT_YUYV */, field=V4L2_FIELD_ANY, bytesperline=0, sizeimage=0, colorspace=V4L2_COLORSPACE_DEFAULT}} => {fmt.pix={width=128, height=128, pixelformat=v4l2_fourcc('Y', 'U', 'Y', 'V') /* V4L2_PIX_FMT_YUYV */, field=V4L2_FIELD_NONE, bytesperline=256, sizeimage=32768, colorspace=V4L2_COLORSPACE_SRGB}}) = 0
ioctl(6, VIDIOC_G_FMT, {type=V4L2_BUF_TYPE_VIDEO_CAPTURE, fmt.pix={width=128, height=128, pixelformat=v4l2_fourcc('Y', 'U', 'Y', 'V') /* V4L2_PIX_FMT_YUYV */, field=V4L2_FIELD_NONE, bytesperline=256, sizeimage=32768, colorspace=V4L2_COLORSPACE_SRGB}}) = 0
ioctl(6, VIDIOC_S_CTRL, {id=V4L2_CID_HFLIP, value=1 => 1}) = 0
ioctl(6, VIDIOC_REQBUFS, {type=V4L2_BUF_TYPE_VIDEO_CAPTURE, memory=V4L2_MEMORY_MMAP, count=1 => 1}) = 0
ioctl(6, VIDIOC_QUERYBUF_TIME32, {type=V4L2_BUF_TYPE_VIDEO_CAPTURE, index=0, memory=V4L2_MEMORY_MMAP, m.offset=0x40000000, length=32768, flags=V4L2_BUF_FLAG_TIMESTAMP_COPY|V4L2_BUF_FLAG_TSTAMP_SRC_EOF, ...}) = 0
ioctl(6, VIDIOC_STREAMON, [V4L2_BUF_TYPE_VIDEO_CAPTURE]) = 0
ioctl(6, VIDIOC_STREAMON, [V4L2_BUF_TYPE_VIDEO_OUTPUT]) = 0
ioctl(6, VIDIOC_QBUF_TIME32, {type=V4L2_BUF_TYPE_VIDEO_OUTPUT, index=0, memory=V4L2_MEMORY_MMAP, m.offset=0, length=32768, flags=V4L2_BUF_FLAG_MAPPED|V4L2_BUF_FLAG_QUEUED|V4L2_BUF_FLAG_TIMESTAMP_COPY|V4L2_BUF_FLAG_TSTAMP_SRC_EOF, bytesused=32768, timestamp={tv_sec=1002, tv_usec=107967}, sequence=0, ...}) = 0
ioctl(6, VIDIOC_QBUF_TIME32, {type=V4L2_BUF_TYPE_VIDEO_OUTPUT, index=1, memory=V4L2_MEMORY_MMAP, m.offset=0x8000, length=32768, flags=V4L2_BUF_FLAG_MAPPED|V4L2_BUF_FLAG_QUEUED|V4L2_BUF_FLAG_TIMESTAMP_COPY|V4L2_BUF_FLAG_TSTAMP_SRC_EOF, bytesused=32768, timestamp={tv_sec=1002, tv_usec=108260}, sequence=0, ...}) = 0
ioctl(6, VIDIOC_QBUF_TIME32, {type=V4L2_BUF_TYPE_VIDEO_OUTPUT, index=2, memory=V4L2_MEMORY_MMAP, m.offset=0x10000, length=32768, flags=V4L2_BUF_FLAG_MAPPED|V4L2_BUF_FLAG_QUEUED|V4L2_BUF_FLAG_TIMESTAMP_COPY|V4L2_BUF_FLAG_TSTAMP_SRC_EOF, bytesused=32768, timestamp={tv_sec=1002, tv_usec=108451}, sequence=0, ...}) = 0
ioctl(6, VIDIOC_QBUF_TIME32, {type=V4L2_BUF_TYPE_VIDEO_CAPTURE, index=0, memory=V4L2_MEMORY_MMAP, m.offset=0x40000000, length=32768, flags=V4L2_BUF_FLAG_MAPPED|V4L2_BUF_FLAG_QUEUED|V4L2_BUF_FLAG_TIMESTAMP_COPY|V4L2_BUF_FLAG_TSTAMP_SRC_EOF, ...}) = 0

the IPU is configured with

0x02600000 CONF                         0x0000'0004
  CSI0_EN                             : false
  CSI1_EN                             : false
  IC_EN                               : true
  IRT_EN                              : false
  DP_EN                               : false
  DI0_EN                              : false
  DI1_EN                              : false
  SMFC_EN                             : false
  DC_EN                               : false
  DMFC_EN                             : false
  SISG_EN                             : false
  VDI_EN                              : false
  IDMAC_DIABLE                        : false
  DMFC_SEL                            : IDMAC
  DMFC_SYNC                           : async
  CSI0_DAT_SOURCE                     : parallel
  CSI1_DAT_SOURCE                     : parallel
  IC_INPUT                            : CSI
  CSI_SEL                             : CSI0

0x0260003c INT_CTRL_EOF_0               0x10c0'0800

0x02600040 INT_CTRL_EOF_1               0x0004'8000

0x02600200 INT_STAT_EOF_0               0x0000'0000

0x02600204 INT_STAT_EOF_1               0x0000'0000

0x02600208 INT_STAT_NFACK_0             0x0000'0800

0x0260020c INT_STAT_NFACK_1             0x0000'0000

0x02600210 INT_STAT_NFB4EOF_0           0x0000'0000

0x02600214 INT_STAT_NFB4EOF_1           0x0000'0000

0x02600218 INT_STAT_EOS_0               0x0000'0000

0x0260021c INT_STAT_EOS_1               0x0000'0000

0x02600220 INT_STAT_9                   0x0000'0000

0x02600224 INT_STAT_10                  0x0000'0000

0x02600228 INT_STAT_EOBND_0             0x0000'0000

0x0260022c INT_STAT_EOBND_1             0x0000'0000

0x02600230 INT_STAT_TH_0                0x0000'0000

0x02600234 INT_STAT_TH_1                0x0000'0000

0x02600238 INT_STAT_15                  0x0000'0000

0x0260023c CUR_BUF_0                    0x0000'0000

0x02600240 CUR_BUF_1                    0x0000'0000

0x02600268 CH_BUF0_RDY0                 0x0040'0800

0x0260026c CH_BUF0_RDY1                 0x0000'0000

0x02600270 CH_BUF1_RDY0                 0x0000'0000

0x02600274 CH_BUF1_RDY1                 0x0000'0000


======================== IPU1-IDMAC ==============================
0x02608000 CONF                         0x0000'002f
  MAX_REQ_READ                        : 7
  WIDPT                               : 1
  RDI                                 : true
  P_ENIAN                             : false
  USED_BUFS_MAX_W                     : 0
  USED_BUFS_EN_W                      : false
  USED_BUFS_MAX_R                     : 0
  USED_BUFS_EN_R                      : false

0x02608004 CH_EN_1                      0x0040'0800

0x02608100 CH_BUSY_1                    0x0000'0000

0x02608104 CH_BUSY_2                    0x0000'0000

======================== IPU1-IC ==============================
0x02620000 CONF                         0x0001'0000
  PRPENC_EN                           : false
  PRPENC_CSC1_EN                      : false
  PRPENC_ROT_EN                       : false
  PRPVF_EN                            : false
  PRPVF_CSC1                          : false
  PRPVF_CSC2                          : false
  PRPVF_CMB                           : false
  PRPVF_ROT_EN                        : false
  PP_EN                               : true
  PP_CSC1                             : false
  PP_CSC2                             : false
  PP_CMB                              : false
  PP_ROT_EN                           : false
  IC_GLB_LOC_A                        : false
  IC_KEY_COLOR_EN                     : false
  RWS_EN                              : false
  CSI_MEM_WR_EN                       : false

0x02620018 IDMAC_1                      0x0040'0024
  CB0_BURST_16                        : burst 8 px
  CB1_BURST_16                        : burst 8 px
  CB2_BURST_16                        : burst 16 px
  CB3_BURST_16                        : burst 8 px
  CB4_BURST_16                        : burst 8 px
  CB5_BURST_16                        : burst 16 px
  CB6_BURST_16                        : burst 8 px
  CB7_BURST_16                        : burst 8 px
  ENC_ROT                             : false
  ENC_FLIP_LR                         : false
  ENC_FLIP_UD                         : false
  VF_ROT                              : false
  VF_FLIP_LR                          : false
  VF_FLIP_UD                          : false
  PP_ROT                              : false
  PP_FLIP_LR                          : false
  PP_FLIP_UD                          : false
  ENC_FLIP_RS                         : false
  VF_FLIP_RS                          : false
  PP_FLIP_RS                          : true

0x0262001c IDMAC_2                      0x07f0'0000
  enc_fr_height                       : 0
  vf_fr_height                        : 0
  pp_fr_height                        : 127

0x02620020 IDMAC_3                      0x07f0'0000
  enc_fr_width                        : 0
  vf_fr_width                         : 0
  pp_fr_width                         : 127

======================== IPU1-CPMEM ==============================
0x027002c0 CH-I#11_0                    0x0001fc0f'e0001800'00000000'00000000'00000000
  XV                                  : 0
  YV                                  : 0
  XB                                  : 0
  YB                                  : 0
  NSB_B                               : false
  CF                                  : even
  SX                                  : 0
  SY                                  : 0
  NS                                  : 0
  SDX                                 : 0
  SM                                  : 0
  SCC                                 : false
  SCE                                 : false
  SDY                                 : 0
  SDRX                                : false
  SDRY                                : false
  BPP                                 : 16 bpp
  DEC_SEL                             : 0-15
  DIM                                 : 2d
  SO                                  : progressive
  BNDM                                : no bands
  BM                                  : no block mode
  ROT                                 : false
  HFLIP                               : false
  VFLIP                               : false
  THE                                 : false
  CAP                                 : false
  CAE                                 : false
  FW                                  : 127
  FH                                  : 127
  EOLI                                : false

0x027002e0 CH-I#11_1                    0x00000000'00003fc0'0103c000'00000000'06027000
  EBA0                                : 0x06027000
  EBA1                                : 0x00000000
  ILO                                 : 0
  NPB                                 : 15
  PFS                                 : interleaved 4:2:2 Y1U1Y2V1
  ALU                                 : false
  ALBM                                : 0
  ID                                  : 0
  THRESHOLD                           : 0
  SLY                                 : 255
  WID0                                : 0
  WID1                                : 0
  WID2                                : 0
  WID3                                : 0
  OFS0                                : 0
  OFS1                                : 0
  OFS2                                : 0
  OFS3                                : 0
  SXYS                                : false
  CRE                                 : false
  DEC_SEL2                            : false

0x02700580 CH-I#22_0                    0x0001fc0f'e1001800'00000000'00000000'00000000
  XV                                  : 0
  YV                                  : 0
  XB                                  : 0
  YB                                  : 0
  NSB_B                               : false
  CF                                  : even
  SX                                  : 0
  SY                                  : 0
  NS                                  : 0
  SDX                                 : 0
  SM                                  : 0
  SCC                                 : false
  SCE                                 : false
  SDY                                 : 0
  SDRX                                : false
  SDRY                                : false
  BPP                                 : 16 bpp
  DEC_SEL                             : 0-15
  DIM                                 : 2d
  SO                                  : progressive
  BNDM                                : no bands
  BM                                  : no block mode
  ROT                                 : false
  HFLIP                               : true
  VFLIP                               : false
  THE                                 : false
  CAP                                 : false
  CAE                                 : false
  FW                                  : 127
  FH                                  : 127
  EOLI                                : false

0x027005a0 CH-I#22_1                    0x00000000'00003fc0'0103c000'00000000'06039000
  EBA0                                : 0x06039000
  EBA1                                : 0x00000000
  ILO                                 : 0
  NPB                                 : 15
  PFS                                 : interleaved 4:2:2 Y1U1Y2V1
  ALU                                 : false
  ALBM                                : 0
  ID                                  : 0
  THRESHOLD                           : 0
  SLY                                 : 255
  WID0                                : 0
  WID1                                : 0
  WID2                                : 0
  WID3                                : 0
  OFS0                                : 0
  OFS1                                : 0
  OFS2                                : 0
  OFS3                                : 0
  SXYS                                : false
  CRE                                 : false
  DEC_SEL2                            : false

 

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‎02-15-2023 07:29 AM
766 Views
ensc
Contributor III

Kernel driver does not activate IPU-PRG when using only the IC but not a display.  PRG must be enabled explicitly.

View solution in original post

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‎02-15-2023 07:29 AM
767 Views
ensc
Contributor III

Kernel driver does not activate IPU-PRG when using only the IC but not a display.  PRG must be enabled explicitly.

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‎01-31-2023 07:35 AM
812 Views
Bio_TICFSL
NXP TechSupport
NXP TechSupport

Hello,

 

Nothing has changed since MX6 and MX6q for IPU, I guess you issue could be the dma, you have to try changing channels and see how its working.

 

Regards

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