Can someone please explain what is the application of the FIFO error Flag (FEF) in the LPI2C Master Status Register (MSR)? If the start condition is always sent before a write/read request in the driver, do we still need its interrupt?
I am asking because I do not use this status flag right now and when I try to clear it by writing 1 it does not clear. Other status flags are clear by writing 1.
Note: I am also NOT using the auto-stop feature i.e., MCFGR1[AUTOSTOP] = 0
You have to reset the FIFO (via the LPI2C::MCR register) before you can clear the FEF flag
Hi @ZohaibAli
This flag is triggered when master starts recieving or sending data without a start condition.
You can read this thread for another reason the flag cold be triggered.
The manual does not specify that this flag is needed for the module to work.
Best Regards, Miguel.