IMXRT1020 with two SDRAM chips.

[nicolasmuratore]

Hi everybody, hope this email finds you well, I would appreciate some help about a proyect that I'm doing, I'm developing a custom board based on IMXRT1020 EVK, with the difference that I'm using two SDRAM chips to add more memory for future software developments, these SDRAM are connected to two independent 512Mbit sectors of the SEMC using two CS:

IMXRT1021DAG5A connected to:

• SDRAM0 IS42S16160J-6TLI (CS0 GPIO_EMC_12)
• SDRAM1 IS42S16160J-6TLI (CS1 GPIO_AD_B1_01)

The software is stored in a uSD card and then (using a DCD file) it is copied on SDRAM to running from there. 

Using one SDRAM (SDRAM0 connected to CS0) and MCUBootutility I can download an image to the uSD with a DCD file and everithing works fine just with one SDRAM:

These are the MCU Settings to use only one SDRAM:

Problem: When I try to use the other SDRAM (CS1) putting the heap and stack there (those are in the BOARD_SDRAM_NCACHE region), it doesn't work any more:

These are the settings to use two SDRAM:

I've attahced the DCD file that works fine with one SDRAM but not for two, this DCD file is modified to send IP commands to the second SDRAM (starting with 84000000 address).

I've validated the connection hardware using a program that running in NOR to test both SDRAM0 and 1, and those work ok, so the hardware not seems to be the problem.

I think that I'm making a mistake with the inicialization process of SEMC to handle two SDRAM on differents sector.

I'm doing different tests trying to find an answer, but I can't find a solution.

Would you have an idea?

Maybe you have an "application note" to share with me about a similar case.

I'm searching on the web but I can't find something similar, usually both SDRAM are used with the same CS sector.

Many thanks in advance. 

[nicolasmuratore]

Hi Jingpan, many thanks for your answer, I didn't try what you say, booting from NOR flash I can initialize from code and use both SDRAM, but not at the same time.

First I initialize, by code, SDRAM0 on CS0, then I do a test first fillin SDRAM0 and then reading it to compare, after that I do the same thing with the other SDRAM1 on CS1, the result is good, but if I try filling the SDRAM0 on CS0 again, the reading loose many bytes, unless I initialize SDRAM0 again.

So seems to be that I'm not initializing the SEMC correctly to use both sectors, CS0 and CS1.

I'm trying but I can´t find the correct way to do it.

About the DCD file, I have a file (attached previously) that I'm using to boot from SDRAM0 added using MCUbootutility, of course it doens't work to add SDRAM1 to my memory map. 

About RT1170, is a different approach, both SDRAM are connected in only one CS sector, adding both 8bits output to a larger resulting 16bit output and 2x256Mbit capacity.   

Many thanks.

[jingpan]

Hi @nicolasmuratore ,

If the DCD is integrated into NOR flash project, can SDRAM2 work? I mean boot from NOR and let ROM bootloader initialize SDRAM by this DCD.

RT1170 EVK has two SDRAM. You can refer to its demo and DCD.

Regards,

Jing

[nicolasmuratore]

Sorry jingpan, I forgot to answer your first question, booting from NOR flash using external DCD bin file (no SDRAM configuration from software) the SDRAM2 (CS1) doesn't work.

I've attached the last DCD file, I'm really breaking my mind with this and I can't find a solution.

Many thanks. 

[jingpan]

Hi @nicolasmuratore,

I'm sorry but reading binary file is really a hard job. Can you make some comments or give a screenshot of the SEMC register table when debugging?

Regards,

Jing

[nicolasmuratore]

Hi Jingpan,

Attached you will find the DCD.bin file in pdf version and commented.

Many thanks.

[jingpan]

Hi @nicolasmuratore ,

I checked your DCD. I can't find problem. Have you used the SEMC demo to set both SDRAM and test them simultaneously?

Regards,

Jing

[nicolasmuratore]

Hi Jingpan, about the DCD file, is a good news that you think it is ok.

About the SEMC demo proyect, yes I can modify it to handle both SDRAM, I do the same process of initialization like DCD file but by software, then using a pointer I can write 4096 bytes and check the information on both memories.

Could be possible that the bootloader has some limitation when we try to boot from SDRAM?

I'm thinking on that because I only use a half of both channels so, maybe it needs a continuous memory map and not to suddenly jump to the next chip select when gets the final of the first SDRAM.

Many thanks for your support.

[jingpan]

Hi @nicolasmuratore ,

I think it is not ROM bootloader's problem. It should be DCD's problem. You can read out SEMC register table after boot from this DCD file. And then compare with the SEMC demo's SEMC register file. I think this can figure out the different.

Regards,

Jing 

[FMA]

Hello, did you find a solution to your problem?

I have quite a similar problem I thought we had solved (https://community.nxp.com/t5/i-MX-RT/SEMC-timing-adjustments-for-SDRAM-design-with-2-chips/m-p/15440...) though memory corruption still happen.

I have 2 32 MB connected to CS0 and CS1. If I configure my design to only use 32MB (using either of those chips), I do not experience any memory corruption. However, as soon as I configure design to run a total 64MB design, memory corruption happens. I cannot detect it using u-boot's internal mtest function on one of the two prototype boards I have though I cannot load my main firmware from SDRAM memory on both cards because of CRC errors detected on it.

[nicolasmuratore · Accepted solution]

Hi FMA, yes I found a solution, like Jingpan said, was a DCD problem.

I've tried with many different DCD files until I've got the correct one.

Now my IMXRT1020 custom board is working with the two SDRAM connected to CS0 and CS1 at the boot stage.

I will attached to this email the DCD file, and the .xml files of the proyect configuration on MCUExpresso.

Seems to be that this configuration is working, but unfortunately I had to leave this proyect by another solution,  so I didn't test it enough to know that is not any memory inconsistency or some trouble related to SDRAM data.

Hope this could help you.