IMX93 M33 core GPIO interrupts

[Vitus]

playing/debugging  the imx93. I have a simple problem, maybe someone can point to what I do wrong here. I want to create an interrupt with a GPIO state change. I use the drivers from NXP, fsl_rpgio.c/h provided with the SDK for the i.MX93)

First I set the MUX:

    IOMUXC_SetPinMux    (IOMUXC_PAD_I2C1_SDA__GPIO1_IO01, 0U);
    IOMUXC_SetPinConfig (IOMUXC_PAD_I2C1_SDA__GPIO1_IO01, 
                         IOMUXC_PAD_DSE(15U) |
                         IOMUXC_PAD_FSEL1(2U) |
                         IOMUXC_PAD_PD_MASK);  

Then I set up the port

rgpio_pin_config_t pin_config = {
      kRGPIO_DigitalInput,
      0,
  };
  GPIO1->PCNS = 0x0;      /* Set PCNS register value to 0x0 to prepare the RGPIO initialization */
  GPIO1->ICNS = 0x03; 
  RGPIO_PinInit(GPIO1, 1, &pin_config);  //sets PDDR
  RGPIO_SetPinInterruptConfig(GPIO1, 1, kRGPIO_InterruptOutput0, kRGPIO_InterruptRisingEdge); //rising edge interrupt
  NVIC_SetPriority(GPIO1_0_IRQn, 3 /*25*/ /*HAL_GPIO_ISR_PRIORITY*/);
  NVIC_EnableIRQ(GPIO1_0_IRQn);

for the interrupt handler I define (Reserved26 seems to be the General Purpose Input/Output 1 interrupt 0. This may be my mistake, as I just guessed this, finding no example/docu )

void Reserved26_IRQHandler()
{
  RGPIO_ClearPinsInterruptFlags(GPIO1, 0, (1<<1));
}

But the interrupt never comes. Did I overlook sth. obvious?

[Manuel_Salas]

Hello @Vitus 

Please change the:

GPIO1->ICNS = 0x03; 

to:

GPIO1->ICNS = 0x00; 

Also, please add to your IRQ:

SDK_ISR_EXIT_BARRIER;

I made a little example using the GPIO2_IO02 as output connected to GPIO2_IO03 configured as an Input with Rising edge IRQ.

In this program, an IRQ will be detected on each rising edge of GPIO2_IO02, Please check the attached.

Also, my IOMUX:

void BOARD_InitPins(void) {                               
    IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO02__GPIO2_IO02, 0U);
    IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO03__GPIO2_IO03, 0U);
    IOMUXC_SetPinMux(IOMUXC_PAD_UART2_RXD__LPUART2_RX, 0U);
    IOMUXC_SetPinMux(IOMUXC_PAD_UART2_TXD__LPUART2_TX, 0U);

    IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO02__GPIO2_IO02, 
                        IOMUXC_PAD_DSE(15U) |
                        IOMUXC_PAD_FSEL1(2U) |
                        IOMUXC_PAD_PD_MASK);
    IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO03__GPIO2_IO03, 
                        //IOMUXC_PAD_DSE(15U) |
                        //IOMUXC_PAD_FSEL1(2U) |
                        IOMUXC_PAD_PD_MASK);
    IOMUXC_SetPinConfig(IOMUXC_PAD_UART2_RXD__LPUART2_RX, 
                        IOMUXC_PAD_PD_MASK);
    IOMUXC_SetPinConfig(IOMUXC_PAD_UART2_TXD__LPUART2_TX, 
                        IOMUXC_PAD_DSE(15U));
}

This is the output of the example:

I hope this example can helps to you.

Best regards,

--... ...--

Salas.