Hi,
Thank you for your interest in NXP Semiconductor products,
1. The Frequency Set-points are defined below and they aren't required to be updated.
Number of FSP. This setting allows the user to select the number of frequency setpoints to include for the Hardware Fast Frequency Change.
2. From your simulation (depending on the memory and the controller, as the transmission line characteristics, the optimum ODT will be determined.
These are the desired ODT impedance in Ohm. Valid values for DDR4=240,120,80,60,40. Valid values for DDR3L=high-impedance,120,60,40. Valid values for LPDDR4=240,120,80,60,40.
3. vTSA performs Virtual Timing Signal Analysis by running tests to determine margins of DDR subsystem.
Diag Write Margin/ Diag Read Margin tests creates virtual data eye diagram for each DQ lanes.
Regards