Hi, experts
We have encounter a display shifting issue when test our board, the screen resolution is 1920x1080, it sometimes has a large offset in the x direction.
The origin image is as follows:
origin image
It is worth noting that the screen does not shift every time when I boot the system. The probability of the screen shifting is about 1/15. The offset of the image on the screen in the x direction is the same every time.
The display related device tree nodes are as following:
```
lcdif1: display-controller@32e80000 {
compatible = "fsl,imx8mp-lcdif";
reg = <0x32e80000 0x10000>;
clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
status = "disabled";
port {
lcdif1_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif1>;
};
};
};
mipi_dsi: dsi@32e60000 {
compatible = "fsl,imx8mp-mipi-dsim";
reg = <0x32e60000 0x400>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
clock-names = "bus_clk", "sclk_mipi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <200000000>, <24000000>;
samsung,pll-clock-frequency = <24000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsim_from_lcdif1: endpoint {
remote-endpoint = <&lcdif1_to_dsim>;
};
};
};
};
&lcdif1 {
status = "okay";
assigned-clocks = <&clk IMX8MP_VIDEO_PLL1_OUT>,
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI>;
assigned-clock-parents = <0>,
<&clk IMX8MP_VIDEO_PLL1_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <1039500000>,
<148500000>,
<500000000>;
};
&mipi_dsi {
status = "okay";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <200000000>, <12000000>;
samsung,pll-clock-frequency = <12000000>;
samsung,burst-clock-frequency = <924000000>;
samsung,esc-clock-frequency = <16000000>;
ports {
port@1 {
reg = <1>;
dsim_to_sn65dsi84: endpoint {
remote-endpoint = <&sn65dsi84_from_dsim>;
};
};
};
};
```
I have dump the registers of the LCDIF and MIPI DSI when the screen is shift, the values are as following:
32e80000: 00000000 ....
32e80004: 00000000 ....
32e80008: 00000000 ....
32e80010: 80000000 ....
32e80014: 04380780 ..8.
32e80018: 005a005a Z.Z.
32e8001c: 000a000a ....
32e80020: 000a001e ....
32e80024: 00010005 ....
32e80028: 00000000 ....
32e80030: 00000001 ....
32e80034: 00000001 ....
32e80200: 04380780 ..8.
32e80208: 00221e00 ..".
32e8020c: b5e00000 ....
32e80210: 00000000 ....
32e80214: 89000000 ....
32e60004: 80100400 ....
32e60008: 00000002 ....
32e6000c: 00000000 ....
32e60010: 91f80008 ....
32e60014: 00ffffff ....
32e60018: 3670707f .pp6
32e6001c: 01e00000 ....
32e60020: 84380780 ..8.
32e60024: f00a000a ....
32e60028: 00440044 D.D.
32e6002c: 02800013 ....
32e60030: 03000400 ....
32e60034: 01000000 ....
32e60038: 8b337fff ..3.
32e6003c: 00000000 ....
32e60040: 00000000 ....
32e60044: ff7fb5aa ....
32e60048: 000001ff ....
32e6004c: 0155541f .TU.
32e60050: 00004040 @@..
32e60078: 00010002 ....
32e60090: 00000000 ....
32e60094: 008049a2 .I..
32e60098: 00000000 ....
32e6009c: 00000000 ....
32e600a0: 000001f4 ....
32e600a4: 00000000 ....
32e600a8: 00000000 ....
32e600ac: 00000000 ....
32e600b0: 00000000 ....
32e600b4: 0000060c ....
32e600b8: 041e0d07 ....
32e600bc: 00050d09 ....
Could you help me see what's wrong on my platform? Thank you very much!
Snow
Best regards
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