IMX8ULP drive strength for SD clock pin

[darko311]

Hello,

I'm having some issues adjusting drive strength for PTD22 pin on IMX8ULP based board.

We're integrating a WiFi module that is interfaced through SDIO. The maximum supported SD clock for the WiFi module is 50MHz. But with that high of a clock, the driver fails to communicate with the module during large file transfers. The culprit looks like to be SD clock signal going to the module that doesn't look too good

Lowering the SD clock to 20 MHz helps with the timeouts and the driver works well, but that also limits the performance of the module and the clock still doesn't look too good on the scope.

 
According to the IMX8ULP TRM, it should be possible to adjust drive strength for the SD clock pin. Setting it to high should help with the clock looking more like a square as it should, but it doesn't seem to do anything.

I changed the pinctrl value from

	pinctrl_usdhc1: usdhc1grp {
		// Try to set drive strength for clock pin to high
		fsl,pins = <
			MX8ULP_PAD_PTD23__SDHC1_CMD	0x3
			MX8ULP_PAD_PTD22__SDHC1_CLK	0x10002
			MX8ULP_PAD_PTD18__SDHC1_D3	0x3
			MX8ULP_PAD_PTD19__SDHC1_D2	0x3
			MX8ULP_PAD_PTD20__SDHC1_D1	0x3
			MX8ULP_PAD_PTD21__SDHC1_D0	0x3
		>;
	};

to

	pinctrl_usdhc1: usdhc1grp {
		// Try to set drive strength for clock pin to high
		fsl,pins = <
			MX8ULP_PAD_PTD23__SDHC1_CMD	0x3
			MX8ULP_PAD_PTD22__SDHC1_CLK	0x10042
			MX8ULP_PAD_PTD18__SDHC1_D3	0x3
			MX8ULP_PAD_PTD19__SDHC1_D2	0x3
			MX8ULP_PAD_PTD20__SDHC1_D1	0x3
			MX8ULP_PAD_PTD21__SDHC1_D0	0x3
		>;
	};

to set DSE bit 6 to 1, but the clock shape remains the same, it doesn't appear to change anything. I tried various other values for the PTD22 pin config but it always looks the same. Only the clock frequency can be changed.
I cross referenced the values with Config tool for i.MX.

I stumbled upon this email from the kernel mailing list
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230625124238.4071717-10-peng.fan@oss.n...

where Peng Fan and/or Haibo Chan state that iomux on imx8ulp doesn't support drive strength configuration. It sure looks like that in my testing.

Could someone please confirm, is this a fact? Is there any other way to set the drive strength for a pin?

Thank you!
Darko

[darko311]

Hello Joseph, thank you for your help!

I tried doing that but unfortunately, I do not see any change on the scope. It looks identical to the dts without DSE bit enabled.

Here's the snippet from imx8ulp-evk.dts file that's used in u-boot

&usdhc0 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc0>;
	pinctrl-1 = <&pinctrl_usdhc0>;
	pinctrl-2 = <&pinctrl_usdhc0>;
	pinctrl-3 = <&pinctrl_usdhc0>;
	non-removable;
	bus-width = <8>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1>;
	pinctrl-2 = <&pinctrl_usdhc1>;
	pinctrl-3 = <&pinctrl_usdhc1>;
	non-removable;
	bus-width = <4>;
	status = "okay";
};

	pinctrl_usdhc0: usdhc0grp {
		fsl,pins = <
			MX8ULP_PAD_PTD1__SDHC0_CMD	0x3
			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10002
			MX8ULP_PAD_PTD10__SDHC0_D0	0x3
			MX8ULP_PAD_PTD9__SDHC0_D1	0x3
			MX8ULP_PAD_PTD8__SDHC0_D2	0x3
			MX8ULP_PAD_PTD7__SDHC0_D3	0x3
			MX8ULP_PAD_PTD6__SDHC0_D4	0x3
			MX8ULP_PAD_PTD5__SDHC0_D5	0x3
			MX8ULP_PAD_PTD4__SDHC0_D6	0x3
			MX8ULP_PAD_PTD3__SDHC0_D7	0x3
			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10002
		>;
	};
	
	pinctrl_usdhc1: usdhc1grp {
		// Try to set drive strength for clock pin to high
		fsl,pins = <
			MX8ULP_PAD_PTD23__SDHC1_CMD	0x3
			MX8ULP_PAD_PTD22__SDHC1_CLK	0x10042
			MX8ULP_PAD_PTD18__SDHC1_D3	0x3
			MX8ULP_PAD_PTD19__SDHC1_D2	0x3
			MX8ULP_PAD_PTD20__SDHC1_D1	0x3
			MX8ULP_PAD_PTD21__SDHC1_D0	0x3
		>;
	};

Have I missed something?

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

He means dynamically, you should update the u-boot DTS for the pin to use DSE=1 and SRE=0, so the pin configuration won't change.

It is recommended to use a high drive strength and a standard slew rate configuration for frequencies higher than 25MHz.

The total loading capacitance of the pin should be minimized (by PCB layout, connected IC input capacity, etc) to achieve better results.

Regards