IMX8ULP GPIO interrupt cross domain

[FrancoHo]

Hi,

For IMX8ULP, it looks like the A35 core can control the input/output of the GPIOs belonging to the M33 domain. But is it possible that the A35 core receives the interrupt from the GPIOs of M33 domain?

[pengyong_zhang · Accepted solution]

Hi @FrancoHo 

Yes, you are right! Use the MU Transmission interrupt signal.

B.R

[pengyong_zhang]

Hi @FrancoHo 

For imx8ulp. M33 domain GPIO used rpmsg, So A35 can receive the  interrupt from the GPIOs of M33 domain.

B.R

[FrancoHo]

Hi @pengyong_zhang, Thank you for the answer. In our application, we directly access the MU instead of the RPMsg protocol. So you mean the GPIO interrupt will first be received by the M33 domain, then use the MU to notify the A35 domain that an interrupt has been triggered, right?