Hello @mirkoardinghi1
You can refer to IMX8ULP Reference Manual in section 2.1.3 Architecture diagram.
There you can see the Domains of cores:

As you can see, the the only peripherals accessible for cortex A are (check dts
ethernet0 = &fec;
gpio4 = &gpiod;
gpio5 = &gpioe;
gpio6 = &gpiof;
i2c4 = &lpi2c4;
i2c5 = &lpi2c5;
i2c6 = &lpi2c6;
i2c7 = &lpi2c7;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
mmc2 = &usdhc2;
serial0 = &lpuart4;
serial1 = &lpuart5;
serial2 = &lpuart6;
serial3 = &lpuart7;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
isi0 = &isi_0;
csi0 = &mipi_csi0;
And here the accesibles for M core (Included GPIO A, B, C and I2S0):

As the peripherals are from different domain (Real time domain for M core and Application domain for A core) all the peripherals are not accessible for A core.
Best regards.
Salas.