It is not stated in JEDEC specification. I think it depends on the features of DDR PHY and Controller.
As I know, IMX8QXP support data bus swapping. I can fill in my data configuration to get corresponding code. Refer to attachment, which is snapped in worksheet (BoardDataBusConfig) of MX8QXP_C0_B0_LPDDR4_RPA_1.2GHz_V15.xlsx.
Similarly, due to layout, I have the requirement of CA swapping. Such as, DDR_DCF00 is configured to CA2_A, I want to configure it as CA5_A.
There are not these information in user guide .