IMX8QM cross connection of the clock signals of i2c_lvds 0/1

[minskey_guo]

Hi, expert,

    I am looking at the imx8qm DTS file in linux-imx kernel git branch imx_4.14.98_2.0.0_ga.  The IMX8qm SoC has two I2C buses for each ldb brdige.   But in the file: arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi, only one I2C of each ldb used.  Strange that  the i2c1_lvds0 is connected to i2c0_clk (IMX8QM_LVDS0_I2C0_CLK)

i2c1_lvds0: i2c@56247000 {      <-========================I2C1
       compatible = "fsl,imx8qm-lpi2c";
       reg = <0x0 0x56247000 0x0 0x1000>;
       interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
       interrupt-parent = <&irqsteer_lvds0>;
       clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>,        <-----------I2C0 ??
       <&clk IMX8QM_LVDS0_I2C0_IPG_CLK>;           <----i2c0
       clock-names = "per", "ipg";
       assigned-clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>;
       assigned-clock-rates = <24000000>;
       power-domains = <&pd_lvds0_i2c0>;
       status = "disabled";
};

i2c1_lvds1: i2c@57247000 {         <============================= i2C1
       compatible = "fsl,imx8qm-lpi2c";
       reg = <0x0 0x57247000 0x0 0x1000>;
       interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
       interrupt-parent = <&irqsteer_lvds1>;
       clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>,     <--- I2C0
       <&clk IMX8QM_LVDS1_I2C0_IPG_CLK>;       <-- I2C0
       clock-names = "per", "ipg";
       assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>;
       assigned-clock-rates = <24000000>;
       power-domains = <&pd_lvds1_i2c0>;
       status = "disabled";
};

I have few questions about this:

      1.  Why the clock signals of i2c are cross connection ?  clocks of i2c0 are connected to i2c1 master ??

      2.  If we change the cross connection,  says connect clocks of i2c0 to i2c0 module,   is there any trouble ? (any bugs in SCU firmware or hardware ??);

      3.  Can the two channels of each ldb bridge display different picture frames independently ? 

      4.  If we want to set different brightness for the two panels'backlight connect to the two channels of the same ldb, how can we do that since there is only one PWM region (lvds0_pwm: pwm@56244000 for lvds0, lvds1_pwm: pwm@57244000 for lvds1) ?

     5.  In the i2c1_lvdsX node,  it says that i2c use interrrupt 9 of irq_steer:

                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;

         If we want to enable  i2c0_lvdsX,  which interrupt number should we use ?

Best Regards,

-minskey 

[sbertrand]

Hi,

minskey.guo@outlook.com‌‌ were you able to use the I2C on LVDS ?

I am facing an issue where we use both I2C on the LVDS block but only I2C0 is responding correctly. I2C1 does not seems to work.

igorpadykov‌ I2C1 on LVDS interface are the ones listed in the device tree and cabled on the im8qm mek. Are those i2c interface supported and functional ?

Thanks,

Stan

[smarter]

Hi ,

    our designed board use i2c0  as lvds i2c bus,how can I modify devicetree to adjust our board ?thank you.

[igorpadykov]

Hi minskey

seems there is some misunderstanding, as i.MX8QM has two lvds modules

with addresses 5724_XXX : I2C0,I2C1 and 5624_XXXX : I2C0,I2C1
described in Table 2-14. Display Interface 1 memory map, Table 2-13. Display Interface 0 memory map

i.MX8QM Reference Manual.

>   3.  Can the two channels of each ldb bridge display different picture frames independently ? 

not possible to support two different display sizes or timings from the same LDB.

In general may be suggested to obtain i.MX8QM Reference Manual from local marketing office.

Note i.MX8QM is not publicly released yet and has limited support.

Best regards
igor
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[sig0912]

Hi Igor,

I have a similar problem where our design uses i2c0 for the lvds0.

Like other people here I don't understand why the node for i2c0_lvds0 is not defined in the file imx8qm-ss-lvds.dtsi?
Only i2c1_lvds0 is defined:

i2c1_lvds0: i2c@56247000 {
  compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
  reg = <0x56247000 0x4000>;
  interrupts = <9>;
  interrupt-parent = <&irqsteer_lvds0>;
  clocks = <&lvds0_i2c0_lpcg 0>,
  <&lvds0_i2c0_lpcg 1>;
  clock-names = "per", "ipg";
  assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
  assigned-clock-rates = <24000000>;
  power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
  status = "disabled";
};

Can I add the definition of the node i2c0_lvds0 in my custom dts this way? Is the interrupt value correct?

&lvds1_subsys {
  i2c0_lvds0: i2c@56246000 {
    compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
    reg = <0x56246000 0x4000>;
    interrupts = <9>;
    interrupt-parent = <&irqsteer_lvds0>;
    clocks = <&lvds0_i2c0_lpcg 0>,
    <&lvds0_i2c0_lpcg 1>;
    clock-names = "per", "ipg";
    assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
    assigned-clock-rates = <24000000>;
    power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
    status = "okay";
  };
};

For now I still can't detect the serializer which is connected on that i2c0.

Thank you,
Ingrid

[sig0912]

Hi,

So I changed the interrupt value to 8 for the i2c0_lvds0 node

Looks like the lvds0 i2c0 is mapped to i2c-4

Still can't detect anything on the LVDS0 I2C0

Any ideas?

Best Regards,
Ingrid