IMX8MQ to IMX8MQ communication using PCIe cross-link

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IMX8MQ to IMX8MQ communication using PCIe cross-link

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Contributor III

Hi NXP Team,

In one of the hardware designs we are planning to establish a communication link between two IMX8MQ processors. For that we are planning to use the PCIe as the communication medium. The reason we are trying to establish a connection using PCIe is to save the PHY space in the circuit.

On the hardware front, we are planning to establish communication using as per the below diagram.

PCIe-PCIe comm.png

  1. Can you please help to verify the hardware connections and check whether this design is feasible or not from the standard point of view? 
  2. Can we get some software reference for this method? (I have already searched the queries in this forum but not able to find the same?  
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NXP TechSupport
NXP TechSupport

Hi  Harshit

yes this design is feasible, also one can look at below link

(as pcie module is similar to i.MX6)

i.MX6Q PCIe EP/RC Validation System 

For software use linux pcie driver described on

i.MX Software and Development Tools | NXP 

or baremetal sdk (1.1.0_iMX6_Platform_SDK.zip) on link SMP Enable in IMX6 

Best regards
igor
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Contributor III

Hi igorpadykov‌,

Thank you for your reply and confirmation of the hardware connections.

We are planning to use the Linux reference here. From the Linux release notes manual I verified that the EP and RC mode support is there in i.MX8MQ processor.

pastedImage_1.png

  1. From the link, you have shared in the above reply specifies that the external clock is not required, we can go with the internal PCIe clock in EP. Please confirm.
  2. In the previous link we got the following information. However, we are not able to access those files. Can you please provide us the same?pastedImage_2.png
  3. In our end application we want to establish full-duplex communication between two processors. (which might not be the video data). How we can build the same?
  4. In the application how we can establish the synchronization between these two reads and write?  Is this something already implemented by NXP?
  5. Will we get a similar throughput on imx8Q as well as mentioned for imx6Q?pastedImage_4.png
  6. With the above connections whether the throughput will be more if we use RGMII interface (instead of PCIe) for communication between two processors? 

Regards.

16 Views
NXP TechSupport
NXP TechSupport

Hi  Harshit

 

1, yes in this case internal PCIe clock can be used.

For other questions please create new threads.

Best regards
igor