SPI communication does not work after an hour of communication start. I wrote a Kernel module with the below dts configurations. I faced two issues, it was not working for the spi max speed beyond 22 Mhz. and the other issue is a byte shift observed in rx side after an hour. no error reported from ret = spi_sync(mvspi, &m); Also when I tried with user space SPI driver, I didn't get it up and running beyond 20Mhz. I believe upto 50Mhz it should not be an issue for spi communication for both the spidev implementation and the KO module with SDMA support. Please support in resolving the above two issues. SPIDEV to run at 40MHz, KO module to run at 40MHz and should not result in byte shifts after a period of communication.
DTS Configurations made:
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x19
MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x19
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x19
>;
};
&ecspi1 {
fsl,spi-num-chipselects = < 1 >;
cs-gpios = <&gpio5 9 0 > ;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 >;
status = "okay";
#address-cells=<1>;
#size-cells=<0>;
};
ecspi1: ecspi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
reg = <0x0 0x30820000 0x0 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
<&clk IMX8MQ_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
