IMX8MP I2C

[lsp89]

I have a secure eeprom (atsha204a) connected to my imx8mp on i2c3.

This part requires 60us of SDA low in order to wake up. There is a RNG driver for this specific chip in the kernel (5.10.72). It attempts to implement this period of the SDA being low, by transmitting a number of zero bytes, based on the frequency that the i2c has been set to operate at. 

I see that the imx_i2c.c driver does not seemlessly send these bytes from the master, instead it will send them byte by byte, waiting for an ACK (at which point the SDA line goes high), even if you set the ignore ACK flag (which is not read in the driver). this means, that the driver that is attempting to emulate a period of SDA low for minimum 60us, using sequential byte transmissions of zero, fails at it's task. I see the driver also supports 'atomic' transfers using DMA. Perhaps this could be achieved using this?

I read on another page that the dma/atomic transfers is not for the imx8m chip (https://community.nxp.com/t5/i-MX-Processors/Using-SDMA-for-I2C-on-i-MX8M-Linux/m-p/886982). I can see there is no dma set up for the peripheral in imx8mp.dtsi.

Is there anyway to achieve this kind seemless i2c transmission on the imx8mp?

[Chavira]

Thank you for contacting NXP Support!

According to the ATSHA204A Datasheet:

The Wake condition requires that either the system processor manually drives the SDA pin low for tWLO,
or that a data byte of 0x00 is transmitted at a clock rate sufficiently slow so that SDA is low for a
the minimum period of tWLO. When the device is awake, the normal processor I2C hardware and/or software
can be used for device communications up to and including the I/O sequence required to put the device
back into low-power (for example sleep) mode.

You only have to set the TXAK bit on the I2Cx_I2CR register to avoid the automatic ACK.

Best Regards!
Chavira