IMX8MP Custome board DDR Calibration failed

leavs · ‎06-29-2023

We designed one board based on IMX8MP EVK, we use 2GB LPDDR4, When I use Mscale DDR Tool to Calibration it, I got the following FAILED error.

PMU: Error: Failed write leveling coarse
PMU: ***** Assertion Error - terminating *****
[Result] FAILED

Can you help to check what will cause this?

I use MT53D512M32D2DS-053 WT:D and I will attahce the script file for you to check.

The whole result like follow,

#################################################

Download is complete
Waiting for the target board boot...

===================hardware_init=====================

********Found PMIC PCA9450**********
hardware_init exit

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:52:12
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 1500MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 2048MB
Density per controller is: 2048MB
Total density detected on the board is: 2048MB
============================================

MX8M-plus: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1500Mhz...
PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x1007 ****
PMU10: Setting boot clock divider to 28
PMU10: PHY TOTALS - NUM_DBYTES 4 NUM_NIBBLES 8 NUM_ANIBS 10
PMU10: CSA=0x01, CSB=0x01, TSTAGES=0x131F, HDTOUT=5, MMISC=0 DRAMFreq=3000MT DramType=LPDDR4
PMU10: Pstate0 MRS MR01_A0=0xD4 MR02_A0=0x2D MR03_A0=0x31 MR11_A0=0x66
PMU10: Pstate0 MRS MR12_A0=0x48 MR13_A0=0x00 MR14_A0=0x48 MR22_A0=0x16
PMU10: Pstate0 MRS MR01_B0=0xD4 MR02_B0=0x2D MR03_B0=0x31 MR11_B0=0x66
PMU10: Pstate0 MRS MR12_B0=0x48 MR13_B0=0x00 MR14_B0=0x48 MR22_B0=0x16
PMU5: CA bitmap dump for cs 0
PMU5: CAA0 ffffffff0000000000000007ffffffffffffffffffffffff
PMU5: CAA1 ffffffff8000000000000003ffffffffffffffffffffffff
PMU5: CAA2 ffffffff8000000000000003ffffffffffffffffffffffff
PMU5: CAA3 fffffffe000000000000000fffffffffffffffffffffffff
PMU5: CAA4 ffffffffe000000000000000ffffffffffffffffffffffff
PMU5: CAA5 ffffffff8000000000000007ffffffffffffffffffffffff
PMU5: CA bitmap dump for cs 0
PMU5: CAB0 fffffffff0000000000000007fffffffffffffffffffffff
PMU5: CAB1 ffffffff8000000000000007ffffffffffffffffffffffff
PMU5: CAB2 ffffffff000000000000001fffffffffffffffffffffffff
PMU5: CAB3 ffffffff8000000000000003ffffffffffffffffffffffff
PMU5: CAB4 ffffffffe000000000000000ffffffffffffffffffffffff
PMU5: CAB5 ffffffffc000000000000003ffffffffffffffffffffffff
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
PMU: Error: Failed write leveling coarse
PMU: ***** Assertion Error - terminating *****
[Result] FAILED

leavs · ‎08-13-2023

Thank you for the help, the issue comes from the hardware, we use one new DDR to resolve this issue.

元の投稿で解決策を見る

leavs · ‎08-13-2023

Thank you for the help, the issue comes from the hardware, we use one new DDR to resolve this issue.

Sanket_Parekh · ‎06-30-2023

Hi @leavs

I hope you are doing well.

Please try changing PhyVref to 0x11.

Could you please provide me with the RPA xlsx sheet and schematic?

It will help to debug & cross-check information about lpddr.

Thanks & Regards,

Sanket Parekh

leavs · ‎06-30-2023

Hi @Sanket_Parekh

Thanks for your quickly reply.

I attached the schematic for LPDDR4 and RPA xlsx sheet.

We use same designe with IMX8MP for LPDDR4, but we use another Micro DDR called MT53D512M32D2DS-053 WT:D, it only have 2GB.

I will try changing PhyVref to 0x11 and back with the result.

leavs · ‎07-02-2023

Hi @Sanket_Parekh

I changed PhyVref to 0x11, the same error and result. Is there other option I can try?

Download is complete
Waiting for the target board boot...

===================hardware_init=====================

********Found PMIC PCA9450**********
hardware_init exit

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:52:12
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 1500MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 2048MB
Density per controller is: 2048MB
Total density detected on the board is: 2048MB
============================================

MX8M-plus: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1500Mhz...
PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x1007 ****
PMU10: Setting boot clock divider to 28
PMU10: PHY TOTALS - NUM_DBYTES 4 NUM_NIBBLES 8 NUM_ANIBS 10
PMU10: CSA=0x01, CSB=0x01, TSTAGES=0x131F, HDTOUT=5, MMISC=0 DRAMFreq=3000MT DramType=LPDDR4
PMU10: Pstate0 MRS MR01_A0=0xD4 MR02_A0=0x2D MR03_A0=0x31 MR11_A0=0x66
PMU10: Pstate0 MRS MR12_A0=0x48 MR13_A0=0x00 MR14_A0=0x48 MR22_A0=0x16
PMU10: Pstate0 MRS MR01_B0=0xD4 MR02_B0=0x2D MR03_B0=0x31 MR11_B0=0x66
PMU10: Pstate0 MRS MR12_B0=0x48 MR13_B0=0x00 MR14_B0=0x48 MR22_B0=0x16
PMU5: CA bitmap dump for cs 0
PMU5: CAA0 ffffffff0000000000000007ffffffffffffffffffffffff
PMU5: CAA1 ffffffff8000000000000003ffffffffffffffffffffffff
PMU5: CAA2 ffffffff8000000000000003ffffffffffffffffffffffff
PMU5: CAA3 fffffffe000000000000000fffffffffffffffffffffffff
PMU5: CAA4 ffffffffe000000000000000ffffffffffffffffffffffff
PMU5: CAA5 ffffffff8000000000000007ffffffffffffffffffffffff
PMU5: CA bitmap dump for cs 0
PMU5: CAB0 fffffffff0000000000000007fffffffffffffffffffffff
PMU5: CAB1 ffffffff8000000000000003ffffffffffffffffffffffff
PMU5: CAB2 ffffffff000000000000001fffffffffffffffffffffffff
PMU5: CAB3 ffffffff8000000000000003ffffffffffffffffffffffff
PMU5: CAB4 ffffffffe000000000000000ffffffffffffffffffffffff
PMU5: CAB5 ffffffffc000000000000007ffffffffffffffffffffffff
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
PMU: Error: Failed write leveling coarse
PMU: ***** Assertion Error - terminating *****
[Result] FAILED