IMX8MN MIPI DSI clock initialization failed

[adab]

Hello,

We are trying to setup the MIPI DSI in order to connect it with a LVDS driver through a MIDI-DSI to LVDS bridge without successfully. The kernel version is 5.10.9 (built with Yocto).

The problem that we are facing, is that when the sn65dsi83 driver is trying to attach to the dsi bus, and then the dsi controller (imx_sec_dsim_drv) try to configure the PLL (in sec_mipi_dsim_config_pll function of the sec-dsim.c driver), it seems that the MIPI clock lines are not in the stop state (the value of the DSIM register is 0x10010f (bit8 is 0)). The following log message is show in dmesg: 

[ 4.258899] imx_sec_dsim_drv 32e10000.dsi_controller: clock is not in stop state
[ 4.258904] imx_sec_dsim_drv 32e10000.dsi_controller: dsim pll config failed: -16

It implies that the sec_mipi_dsim_bridge_enable function (in the sec-dsim.c driver too), return with error before configure the dphy timings, clocks and prepare the panel. When we try to get the fb configuration with fbset, only the panel resolution is available but not the display timings.

mode "1024x600-0"
# 0.000 MHz, H: 0.000 kHz, V: 0.000 Hz
geometry 1024 600 1024 600 32
timings 0 0 0 0 0 0 0
accel true
rgba 8/16,8/8,8/0,0/0
endmode

In order to check where the DSIM_STATUS register changes to the wrong state (not in HP11 mode) during the initialization, we have monitorized its value during this process. The register changes after execute the drm_bridge_attach(encoder, next, bridge, flags) method (which execute the sn65dsi83_bridge_attach) method in the sn65dsi83_drv.c from 0x10010f to 0x1002f0.

Besides we have measured the MIPI_CLK line and the reset gpio of the sn65dsi83 during the MIPI configuration process. Attached is the screenshot where you can check, the CLK line is following to the reset signal and its level. Is it the expected behavior?

In the following lines you can check the most relevant nodes of in the device tree the lcdif and mipi_dsi nodes plus LVDS bridge (as an I2C sub-node) with the panel timing configuration.

&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";

dsi_lvds_bridge: sn65dsi84@2c {
compatible = "ti,sn65dsi83";
reg = <0x2c>;
ti,dsi-lanes = <4>;
ti,lvds-format = <2>;
ti,lvds-bpp = <24>;
ti,width-mm = <154>;
ti,height-mm = <85>;
ti,burst-mode = <1>;
ti,de-neg-polarity = <1>;
enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
enable-panel-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds>;
status = "okay";
display-timings {
native-mode = <&lvds_mi0700bnt>;
.............................
.............................
}
port {
dsi_lvds_bridge_in: endpoint {
remote-endpoint = <&mipi_dsi_lvds_out>;
};
};

&lcdif {
status = "okay";
};
&mipi_dsi {
status = "okay";

port {
mipi_dsi_lvds_out: endpoint {
remote-endpoint = <&dsi_lvds_bridge_in>;
attach-bridge;
};
};
};

}

Attached you can find the screenshots of the CLK signal during the initialization and the enable gpio of the MIPI to LVDS bridge and the full dmesg log during the initialization. 

Thank you in advance for your support!

Best regards.
Alejandro

[dipak290485]

Hello,

I have facing same issue. Can You send me your sn65dsi83 driver code ?

Your issue was resolved ?