IMX8MM SAI3 slave, codec is master

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IMX8MM SAI3 slave, codec is master

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triedgetech
Contributor III

Codec WM8904 is connected to imx via i2s and i2c, i2s (SAI3) connection is as follows:

Screenshot_20220516_105303.jpg

MCLK pin on codec has 12.288Mhz oscillator.

How do I configure device tree for SAI3 to work in slave mode?

These are the default parameters in device tree:

 

 

			sai3: sai@30030000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
				reg = <0x30030000 0x10000>;
				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
					 <&clk IMX8MM_CLK_SAI3_ROOT>,
					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

 

 

 

 

&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "disabled";
};

 

 

 

 

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC	0xd6
			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK	0xd6
			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6
			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
		>;
	};

 

 

Relevant codec entries:

 

 

sound {
      compatible = "fsl,imx-audio-wm8904";
      model = "imx-wm8904";
      sai-controllers = <&sai3 &sai3>;
      cpu-dai = <&sai3>;
      audio-codec = <&wm8904>;
      codec-master;
      audio-routing =
        "Headphone Jack", "HPOUTR",
        "Headphone Jack", "HPOUTL",
        "IN2L", "Line In Jack",
        "IN2R", "Line In Jack",
        "Mic Jack", "MICBIAS",
        "IN1L", "Mic Jack",
        "IN1R", "Mic Jack";
  };

 

 

 

 

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";


  wm8904: wm8904@1a {
	  compatible = "wlf,wm8904";
	  reg = <0x1a>;
	  clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
	  clock-names = "mclk";
  };
};

 

 

This seems to work, I can record sound from microphone, however there are issues. Right channel on codec has periodic clicking sounds, and occasionally left and right channel get swapped during long recording. I measured BCLK line on scope, and it shows 1.536Mhz, which corresponds to default register settings in WM8904. WM8904 has SYSCLK = MCLK/2 = 6.144Mhz

BCLK = SYSCLK/4 = 1.536Mhz

I feel like I can just delete most entries under SAI3 since they're written for the case when SAI3 is master on imx side, right? I don't need any values for "assigned clock rates" under &SAI3 node, since BCLK is received from WM8904.

In this thread, guy from NXP said that TXC stays the same both for master/slave mode on imx side. So my i2s connection is correct, right?

I did notice that when I use a level shifter to 3.3V for the i2c2 that the codec uses between itself and CPU, the clicks go away. So my question is: why would direct 1.8V &i2c2 (which is i2c1 actually) connection between codec and CPU (without level shifter) cause clicks on the recorded audio file into an internal emmc memory, if something concurrently is being written onto external SD card (USDHC2 interface).

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triedgetech
Contributor III

In their examples, CPU is master, that's not the case with me

setting

 

clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;

 

 means WM codec will be in slave mode and expect clock on SAI3 bclk line, no?

 

Also, does the parameter:

 

&sai3 {
	fsl,sai-mclk-direction-output;
}

mean the CPU is master, and therefore outputs clk on SAI3 to the codec?? What if I want the opposite? I know for sure that my WM codec is master, which uses external mems oscillator on its mclk pin, and I want CPU side to accept clock via BCLK on its i2s (SAI3) interface?

 

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