IMX8MM PCIe CLK

[pet_r_off]

Hi everyone!

I`m developing PCIe driver for QNX and strugglilng a problem with having access to PCIE controller regisers (i think that some of clock lanes not enabled).

Linux log prints me: [ 1.273916] imx6q-pcie 33800000.pcie: PCIe PLL locked after 0 us.
So, my QNX driver founded on https://github.com/nxp-imx/linux-imx/blob/imx_5.4.70_2.3.0/drivers/pci/controller/dwc/pci-imx6.c prints me → PCIe PLL lock timeout.

The simple write to IMX8MM_CLK_PCIE1_ROOT (CCGR37) register doesn`t make any difference.

Is there any special initialization sequence for CCM or for PCIe Controller?

Thanks!

[JorgeCas]

Hello, I hope you are doing well.

On the CCGR interface, before a clock root goes to on–chip peripherals, the clock root is distributed through low power clock gates (LPCG). These LPCG are implemented to automatically perform clock shutdown when a domain enters and leaves a low-power state.

There are four levels of low-power modes in a logic domain:
• Not needed
• Needed in RUN
• Needed in RUN and WAIT
• Needed in RUN, WAIT, and STOP

CCM only takes action while domain status are switching between STOP (DEEP SLEEP mode is considered the same as STOP). There are 4 domains that can be assigned. Any CPU platform can be assigned to any domain by RDC. If a domain is empty, the domain is considered as STOP.

Best regards.

[pet_r_off]

@JorgeCas, thanks for your answer.

Well, It doesn`t work. Maybe I`m doing smth wrong?

Dumping RDC registers in Linux shows that they are in default state as in Reference Manual.

0x303d0208 -> RDC_MDA2

0x303d0560 -> RDC_PDAP88

[root@imx8mm_uq7 ~]#
[root@imx8mm_uq7 ~]# devmem 0x303d0208
0x00000000
[root@imx8mm_uq7 ~]# devmem 0x303d0560
0x000000FF
[root@imx8mm_uq7 ~]#

So, maybe it is not necessary to configure them?