I use a custom board with i.MX8MM and AS4C512M16D4-75BCN. Electrical control is fine, and an x-ray of soldering is fine. but I have trouble with DDR. RPA file with my setting and schematic attached.
Log from i.MX/Mscale DDR Tool. v3.10
Downloading file 'bin\ddr4_train1d_string.bin' ..Done
Downloading file 'bin\ddr4_train2d_string.bin' ..Done
Downloading file 'bin\ddr4_imem_1d.bin' ..Done
Downloading file 'bin\ddr4_dmem_1d.bin' ..Done
Downloading file 'bin\ddr4_imem_2d.bin' ..Done
Downloading file 'bin\ddr4_dmem_2d.bin' ..Done
Downloading IVT header...Done
Downloading file 'bin\m845s_ddr_stress_test.bin' ...Done
Download is complete
Waiting for the target board boot...
I2C_I2SR(0x30a2000c):0x93
bus is not ready
hardware_init exit
*************************************************************************
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MX8 DDR Stress Test V3.10
Built on Feb 5 2020 13:04:09
*************************************************************************
--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x93d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122
- MMU and cache setup complete
*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 1000MHz
============================================
DDR configuration
DDR type is DDR4
Data width: 16, bank num: 8
For DDR4, bank num is the total of 2 bank groups and 4 banks per group
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 1024MB
Density per controller is: 1024MB
Total density detected on the board is: 1024MB
============================================
MX8M-mini: Cortex-A53 is found
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============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @800Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
PMU: Error: dbyte 0 lane 0 failed read deskew
PMU: ***** Assertion Error - terminating *****
[Result] FAILED
What does mean that error? Give me any tips, please.
