IMX8M dual ddr tool stress test error

[mimi05633]

We have a board with IMX8M dual and lpddr4 (part number is Micron MT53E768M32D4DT-053 WT:E). When we modified MX8M_LPDDR4_RPA_v24.xlsx and used MX8M_ddr_tool software to check our memory design, the test report an error:

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Downloading file 'bin\lpddr4_train1d_string.bin' ..Done

Downloading file 'bin\lpddr4_train2d_string.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_1d_imem.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_1d_dmem.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_2d_imem.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_2d_dmem.bin' ..Done

Downloading IVT header...Done
Downloading file 'bin\m850_ddr_stress_test.bin' ...Done

Download is complete
Waiting for the target board boot...
PF0100 is not found: ID=0x0

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MX8 DDR Stress Test V3.10
Built on Feb 5 2020 14:08:44
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--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x91d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

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ARM clock(CA53) rate: 800MHz
DDR Clock: 1600MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 1
Density per chip select: 1536MB
Density per controller is: 3072MB
Total density detected on the board is: 3072MB
============================================

MX8M: Cortex-A53 is found

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============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1600Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @200Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @50Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @1600Mhz...
[Process] End of initialization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Result] PASS

============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@1600MHz.......Pass
Verifying DDR frequency point1@200MHz.......Pass
Verifying DDR frequency point2@50MHz.......Pass
[Result] OK

============ Step 3: DDR parameters processing... ============
[Result] Done

Success: DDR Calibration completed!!!
DDR Stress Test Iteration 1
--------------------------------
--Running DDR test on region 1--
--------------------------------

t0.1: data is addr test
...Address of failure: 0x00000000A0000000
Data read was: 0x0000000093000000
But pattern was: 0x0000000040000000

Any one can tell me what's the error meaning?

Can the lpddr4 use on imx8m board?

Attach RPA excel, ddr script and lpddr4 sdram.

Thanks.

Minying

[igorpadykov]

Hi

>Any one can tell me what's the error meaning?

this error means that ddr test wrote 0x0000000040000000 on
address 0x00000000A0000000 and expects to read the same value.
Instead it read 0x0000000093000000. This may be hardware error or
one can tweak "BoardDataBusConfig" in RPA tool.

Best regards
igor

[mimi05633]

Hi Igor,

Thank you for your reply. We have already checked that the "BoardDataBusConfig" tab does not need to tweak on our board. Is there v24 "Register Configuration" reference values of the DDR(part number:MT53E768M32D4DT-053 WT:E) can provide?

We try to modify Clock Cycle Freq to 800 or 1600 MHz, but stress test fail in t0.1 item.

After we modify Clock Cycle Freq to 200 MHz, stress test can success. We enable PLL by-pass and boot-up hang. Sometimes, our board hang up at console log "[ OK ] Started Update UTMP about System Runlevel Changes.", "imx8mqevk login:", or crash by kernel panic.

Thanks.

Minying

[igorpadykov · Accepted solution]

Hi Minying

if test fails at high frequencies this may be due to board layout,

please recheck sect.3.4. DDR design recommendations

i.MX8M Hardware Developer’s Guide

Also one can try to tweak drive strength through RPA tool.

Best regards
igor

[CHETHANA_RAO]

Hi Igor,

In one of our design we are using MIMX8MQ6CVAHZAB and we observed that DDR stress test failing at frequencies >=1600MHz,
But even if we decrease the frequency by 1Hz,DDR stress test will pass.
(For any frequency below 1600MHz stress test will pass(viz.1599.999999MHz) but for frequencies >=1600MHz it will fail.)
Our observations goes like this.(For 1600MHz & 1599.999999MHz).

Could you please help us to resolve this.

Thanks & Regards,

Chethana

[mimi05633]

Hi Igor,

Sorry to late response. Thanks for your reply. We will check board layout first.

Thank you.

Minying