IMX8M Plus - LVDS protocols and speaker design

[YoavBenita]

Hi,

I would like to use the LVDS outputs for communication between IMX8M plus to FPGA.

I have free 4 lanes and I want to use LVDS0 lines: 1 CLK and 3 DATA.

Is there available SDK for bi directional data transfer protocols ?

I am looking for a way to transfer the data over LVDS at a rate of approximately 100MBPS.

In addition, I need to design speakers for this IMX, is there a sample of design for this processor ?

It can be mono/stereo and low power (max 250mW).

[JorgeCas]

Dear Yoav Benita,

iMX8MP supports LVDS Tx display, Pixel Mapper and it is only unidirectional (output).

For low power speaker design, you can use as a reference the codec that is present on iMX8MP EVK board with WM8960 codec that it is capable to handle 1W per channel (8Ω BTL). You can check more details about this on the attached pdf file.

Best regards.

[YoavBenita]

Hi,

My IMX will compress (264/265) video from two cameras and stream the data to FPGA.

The video from the cameras can be: 30/24fps@2592x1944  or 60fps@1080P/720P.

How do you recommend to stream the compress data from these cameras to the FPGA?

[JorgeCas]

Dear Yoav Benita,
On that case, if your FPGA is able to work as a display to take the data from iMX processor it could be possible to transfer data on that way. Single channel (4 lanes) supports resolutions up to 1366x768p60 and dual asynchronous channels (8 data, 2 clocks) supports resolutions above 1366x768p60, up to 1080p60.
Best regards.

[YoavBenita]

Hi,

The data that will be streaming is the output from H265 compression and the FPGA will be able to receive this data.

But, I have only free 4 lanes of LVDS on the FPGA, so the lanes that will be connected are 3 DATA and 1 CLK. Is it OK ? Does the IMX support a protocol of 3+1 ?

[JorgeCas]

Dear Yoav Benita,

Yes, it is correct to connect 3 DATA and 1 CLK lines, that is the protocol supported by i.MX with resolutions up to 1366x768p60.

Best regards.