IMX8M Mini: Sharing GPIO block between A53 and M4

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IMX8M Mini: Sharing GPIO block between A53 and M4

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sergei_p
Contributor III

Hello,

We have a IMX8M Mini project where the GPIOs are involved with both FreeRTOS on M4 and with Linux on Cortex-A53. On IMX8M Mini, a single GPIO register controls all 32 pins from this GPIO block, so accessing the same register from both sides would be a classic race condition example.

I wonder, is there a solution which would allow simultaneous access to the different GPIO pins in the same GPIO block from M4 and from A53? Or reserving the whole GPIO block to a single core is the only solution?

Thanks!

Regards,

Sergei

5 Replies

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craigmcqueenir
Contributor II

I encountered this same issue. My M4 code can read GPIOs just fine. But I wanted to write to some GPIOs also from the M4, but it seems that GPIO writes to the same block from the Linux kernel GPIO driver were overwriting the changes that the M4 made.

In my case, I used RPmsg so the M4 code would request my custom Linux driver to write the GPIOs for it. That works fine in my case because I don't need hard real-time timing for GPIOs.

I guess if your M4 code needs hard-real-time timing, the alternatives would be:

  • Design your hardware so each GPIO block is to be written by the A53 core, or the M4 core, but not both. For a GPIO block that is written by the M4 core, remove its normal GPIO definition from the device tree for Linux.
  • Or, if your hardware design unavoidably has a GPIO block that must be written by both A53 and M4, make a Linux kernel driver that provides for writing those GPIOs via RPmsg to your M4 code, rather than directly writing to the GPIO (see NXP's sample driver gpio-imx-rpmsg.c).
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anurag16doshi
Contributor II

what could be the another solution for this problem instead of semaphores?

i am using GPIO1,24 as interrupt pin on m7 core while a53 core is using same GPIO(GPIO1,some other pin) for PMIC.

hence, when only m7 core is running ,i am getting the interrupt on pin but as soon as a53 boots up,interrupt pin stop working.

guide me to resolve this issue.

TIA,

Anurag

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Sergei

you are right, there are no special hardware options to allow simultaneous access to the different GPIO

pins in the same GPIO. In general one can use software semaphores or other common options

for sharing peripherals.

Best regards
igor
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sergei_p
Contributor III

Thanks, Igor. If such example exists in the NXP FreeRTOS projects, could you please point out to example of such synchronization?

Regards,

Sergei

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igorpadykov
NXP TechSupport
NXP TechSupport

one can look at sect.2.8 Remote Processor Messaging Linux Manual

in Linux L4.14.98_2.0.0 Documentation

Best regards
igor

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