Hi @timur_kh,
1. These because usually for routing the board is easier and cheaper to connect differently DQ nodes, but this must be corrected once you build your board before you boot up your board you will need to build your own image and specify the DDR parameters you use on this one, and one of them maybe is the different DQ lines, refer to the next link for more info:
i.MX 8M Family DDR Tool Release - NXP Community

2. In the Hardware design guide is not counted as this could vary from customer to customer, not all of them will select the same so you will have to look for the specific info on the DDR datasheet.
3. Usually we use the Allegro tool by enabling the Z-Axis Delay in “Setup - Constraints -
Modes”. You can find more relatable info on the next link: DDR design recommendations.
If there is something more I can help you please let me know.
Regards,
Israel.