IMX8 eMMC CMD timing

[reickhoff]

Using the IMX8SXL with HS400 @167MHz

- The table only calls out SDR50 for setup and hold is this valid for SDR104?

- Can you confirm that we are understanding our plots (below) correctly? the cursors should show a setup of ~ 4.68ns (pass) and a hold of ~1.12ns (fail). Everything has been working fine, and we are confident in our constraint routing from NXP.

We also got the clock, cmd, and strobe captured on one plot

BLUE=CLK   /   ORANGE=STROBE   /   YELLOW=CMD

[Alejandro_Salas]

Hello!

The uSDHC Input Setup Time and uSDHC Input HoldTime for SDR50  and SDR104 should be the same for the IMX8DXL (I guess you are using it). Answering your question, yes, your understanding is the correct.

Best regards @reickhoff .

[reickhoff]

The design is working though so, is there a violation? it doesn't make sense that the JEDEC standard calls out that they are edge aligned, but then the processor needs a setup and hold time.

Can you please help me understand this?

[Alejandro_Salas]

Hello!

In datasheet the SDR104 mode the timing parameters are defined with the SCK as a reference. But the CMD must be referenced to STROBE, please check the figure 10.10.3 from JESD84-B51 and table 218 HS400 CMD RESPONSE TIMING.

Conclusion, please refer to the JESD84-B51 and not to datasheet because I believe in datasheet is a typo.

Best regards!

[reickhoff]

To confirm, you are saying there is a datasheet typo and that our timing looks correct?

Thanks

[Alejandro_Salas]

That is correct, and your timings looks OK according to the JESD84-B51.

Best regards.

[reickhoff]

So there is a violation? how is that possible if the data is coming back sync'd with the strobe and we have adhered to the routing constraints?